Technique for inter-procedural memory address space optimization in GPU computing compiler

Abstract

A device compiler and linker is configured to optimize program code of a co-processor enabled application by resolving generic memory access operations within that program code to target specific memory spaces. In situations where a generic memory access operation cannot be resolved and may target constant memory, constant variables associated with those generic memory access operations are transferred to reside in global memory.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims the benefit of U.S. provisional patent application titled “Method for Inter-Procedural Memory Space Optimization in GPU Computing Compiler” filed on Nov. 7, 2011 and having Ser. No. 61 / 556,782. The entire content of the foregoing application is hereby incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention generally relates to graphics processing unit (GPU) computing compilers, and, more specifically, to a technique for inter-procedural memory address space optimization in a GPU computing compiler.[0004]2. Description of the Related Art[0005]Graphics processing units (GPUs) have evolved over time to support a wide range of operations beyond graphics-oriented operations. In fact, a modern GPU may be capable of executing arbitrary program instructions. Such a GPU typically includes a compiler that compiles program instructions for execution on one or more...

AI Technical Summary

Benefits of technology

The disclosed technique improves the performance of applications by reducing the need for a graphics processing unit to resolve memory access operations at run time. This saves resources and speeds up the execution of the application. Additionally, the graphics processing unit can optimize the program code by re-ordering memory access and analyzing aliases, which further improves execution speed.

Problems solved by technology

However, a given memory access operation targeting a given memory address may not specify any particular memory space.

Relying on the tagging approach described above is problematic for two reasons.

First, reading a tag for each memory access operation is a costly operation and wastes GPU resources.

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