Testing integrated circuits using few test probes

a technology of integrated circuits and test probes, applied in the field of integrated circuits, can solve the problems of reducing the number of probes needed, reducing the number of input/output contact pads, and increasing the risk of scrubbing

Active Publication Date: 2013-05-16
STMICROELECTRONICS SRL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach minimizes the risk of pad damage, enhances testing efficiency, and reduces the overall cost of the test system by requiring fewer and less expensive probes, while maintaining reliable test results.

Problems solved by technology

However, this type of test system has several limitations.
For example, there is the risk of damaging the contact pads of the dies under test.
As known, a contact pad consists of an enlarged metallization region of the IC; when the tip of the mechanical probes touches the pads, there is always the risk that one or more of the pads are damaged by scrubbing, and the likelihood that this happens increases with the number of probes.
Also, the parallel-testing capability is relatively low: indeed, when several dies at a time have to be tested, the number of mechanical probes significantly increases; fabricating probe cards with many probes is not an easy task, and the finite dimensions of the probes pose a physical limit to the density of probes per unit area.
Moreover, the higher the number of probes required, the more probable it is that the electrical contacts between the pads of the ICs under test and the mechanical probes are not good, and electrical discontinuities may take place, which affect the test results.
Furthermore, when the contact pads are very close to each other (a situation frequently encountered due to the constant increase in integration scale and size shrinking), it is very difficult to ensure a good physical contact of the mechanical probes with the contact pads.
Such a problem is emphasized when the pads are small in size and / or a large number thereof is present on each die.
In addition, the mechanical probes are very expensive, thus producing probe cards with several probes negatively contributes to the increase of the overall cost of the test system, and eventually of the ICs.

Method used

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  • Testing integrated circuits using few test probes
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Embodiment Construction

[0045]Throughout the following description, identical or similar elements in the drawings are denoted by same reference numerals.

[0046]Referring to FIG. 1, a block diagram of a test system 100 according to an embodiment of the present invention is schematically shown. The test system 100 is adapted to perform the wafer-level testing of a plurality (for example, hundreds) of IC dies 105 belonging to a semiconductor wafer 110, prior to the dicing thereof into individual chips.

[0047]The specific type of IC 115 integrated on the dies 105 is not limitative to the present invention; in particular, and merely by way of example, the ICs 115 may be or include memory devices, microprocessors or microcontrollers, Digital Signal Processors (DSPs), digital logic circuits, Application Specific Integrated Circuits (ASICs), Field Programmable Gate arrays (FPGAs), analog circuits, RF circuits, MEMS (Micro Electro Mechanical Systems).

[0048]For testing the ICs 115 on the dies 105 in order to assess th...

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Abstract

A method of testing integrated circuits, including establishing at least a first physical communication channel between a test equipment and an integrated circuit under test by having at least a first probe of the test equipment contacting a corresponding physical contact terminal of the integrated circuit under test; having the test equipment and the integrated circuit under test exchange, over said first physical communication channel, at least two signals selected from the group including at least two test stimuli and at least two test response signals, wherein said at least two signals are exchanged by means of at least one modulated carrier wave modulated by the at least two signals.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application is a division of U.S. patent application Ser. No. 12 / 398,148, filed on Mar. 4, 2009, and also a continuation of U.S. patent application Ser. No. 12 / 982753, filed Dec. 30, 2010, which applications claim the priority benefit of Italian patent application number MI2008A00365, filed on Mar. 5, 2008, which applications are hereby incorporated by reference to the maximum extent allowable by law.BACKGROUND[0002]1. Technical Field[0003]The present invention relates to the field of Integrated Circuits (ICs), and particularly to methods and systems for IC testing.[0004]2. Discussion of the Related Art[0005]ICs are typically manufactured many at a time in the form of dies on a semiconductor material wafer. After manufacturing, the semiconductor wafer is diced, so as to obtain a plurality of individual IC chips.[0006]Before being packaged and shipped to the customers, and installed in various electronic systems, the individual ICs ne...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): G01R31/28
CPCG01R31/3172G01R31/31905G01R31/31926G01R31/2851H01L22/30H01L2924/1461H01L2224/16H01L2924/00G01R31/2841
InventorPAGANI, ALBERTO
OwnerSTMICROELECTRONICS SRL