Electrostatic discharge (ESD) protection device

Abstract

An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes an epitaxy layer disposed on a semiconductor substrate. An isolation pattern is disposed on the epitaxy layer to define a first active region and a second active region, which are surrounded by a first well region. A gate is disposed on the isolation pattern. A first doped region and a second doped region are disposed in the first active region and the second active region, respectively. A drain doped region is disposed in the first doped region. A source doped region and a first pick-up doped region are disposed in the second doped region. A source contact plug having an extended portion connects to the source doped region. A ratio of an area of the extended portion covering the first pick-up doped region to an area of first pick-up doped region is between zero and one.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to an electrostatic discharge (ESD) protection device, and in particular, to an electrostatic discharge (ESD) protection device with the ability to adjust holding voltage and trigger voltage.[0003]2. Description of the Related Art[0004]In conventional high voltage device processes, a holding voltage of an electrostatic discharge (ESD) protection device usually is not larger than an operation voltage (VDD) of a device. Therefore, when integrated circuit devices are operated under normal operating conditions, unwanted transients, such as current and voltage surges, result in latch-up events which damage devices. However, the conventional ESD protection device is improved to increase the holding voltage, the trigger voltage simultaneously increases. Therefore, the conventional ESD protection device with improved holding voltage still can not protect the internal circuits of the device.[0005]Th...

AI Technical Summary

Benefits of technology

The patent text describes an electrostatic discharge (ESD) protection device used in semiconductor devices. The device includes a semiconductor substrate, an epitaxy layer, and an isolation pattern. It also includes a gate, first and second doped regions, and a drain doped region. The technical effects of the device include improved protection against electrostatic discharge, reduced device size, and improved performance.

Problems solved by technology

Therefore, when integrated circuit devices are operated under normal operating conditions, unwanted transients, such as current and voltage surges, result in latch-up events which damage devices.

Therefore, the conventional ESD protection device with improved holding voltage still can not protect the internal circuits of the device.

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