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Using Fast Anneal to Form Uniform Ni(Pt)Si(Ge) Contacts on SiGe Layer

a sige layer and fast anneal technology, applied in the field of sige formation, can solve the problems of severe stress loss or junction leakage, bad interface morphology, and even worse problems

Inactive Publication Date: 2014-02-27
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This patent describes a method for making a smooth silicide without the use of a cap layer. The method involves depositing a silicide metal on a semiconductor material and annealing it at a high temperature for a short time to form silicide contacts on the semiconductor material. This process can be used in the fabrication of field-effect transistors, where the silicide contacts are important in making the device function properly. The resulting device has smoother contacts, which can improve its performance.

Problems solved by technology

Nickel platinum (NiPt) silicide is the standard contact metal to the SiGe, however NiPt—SiGe reaction under normal rapid thermal anneal (RTA) results in bad interface morphology (silicide spikes).
Silicide spikes into the SiGe source / drain may cause severe stress loss or junction leakage.
This bad interface morphology issue becomes even worse when the percentage of germanium (Ge) is increased.
However, employing a cap layer in a fabrication process flow increases both production complexity and cost.

Method used

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  • Using Fast Anneal to Form Uniform Ni(Pt)Si(Ge) Contacts on SiGe Layer
  • Using Fast Anneal to Form Uniform Ni(Pt)Si(Ge) Contacts on SiGe Layer
  • Using Fast Anneal to Form Uniform Ni(Pt)Si(Ge) Contacts on SiGe Layer

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Embodiment Construction

[0023]Provided herein are techniques for forming a metal (such as, but not limited to, nickel platinum (NiPt) silicide) on a silicon germanium (SiGe) material which avoid interface morphology issues commonly associated with metal silicide formation on a SiGe material (see above) without the use of a cap layer, which advantageously lowers the complexity and cost of the fabrication process as compared to conventional processes. Namely, in the present techniques a fast anneal (flash anneal or laser anneal) is employed rather than a conventional rapid thermal anneal to form metal silicide on SiGe (with no cap layer). The result (as provided in detail below) is a very smooth metal silicide.

[0024]An overview of the present techniques will first be provided by way of reference to FIGS. 1-3, followed by an exemplary implementation of the present techniques to form source and drain contacts in an exemplary field-effect transistor (FET) device illustrated by way of reference to FIGS. 4-7. FIG...

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Abstract

Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a cap layer-free method for forming a silicide is provided. The method includes the following steps. A semiconductor material selected from: silicon and silicon germanium is provided. At least one silicide metal is deposited on the semiconductor material. The semiconductor material and the at least one silicide metal are annealed at a temperature of from about 400° C. to about 800° C. for a duration of less than or equal to about 10 milliseconds to form the silicide. A FET device and a method for fabricating a FET device are also provided.

Description

FIELD OF THE INVENTION[0001]The present invention relates to silicide formation and more particularly, to techniques for forming a smooth silicide without the use of a cap layer.BACKGROUND OF THE INVENTION[0002]Embedded silicon germanium (SiGe) has recently been used as the source / drain material to boost channel hole mobility (due to the stress induced by lattice mismatch). Nickel platinum (NiPt) silicide is the standard contact metal to the SiGe, however NiPt—SiGe reaction under normal rapid thermal anneal (RTA) results in bad interface morphology (silicide spikes).[0003]Silicide spikes into the SiGe source / drain may cause severe stress loss or junction leakage. This bad interface morphology issue becomes even worse when the percentage of germanium (Ge) is increased.[0004]Conventional approaches to deal with the problem include using a silicon (Si) or SiGe cap layer with a lower percentage of Ge in order to improve the surface morphology. Namely, the cap layer reacts with the NiPt ...

Claims

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Application Information

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IPC IPC(8): H01L21/3205H01L21/336
CPCH01L21/32053H01L21/321H01L29/665H01L29/7848H01L21/28518H01L29/45H01L29/66628H01L29/66636
Inventor NEWBURY, JOSEPH S.RODBELL, KENNETH PARKERZHANG, ZHENZHU, YU
Owner GLOBALFOUNDRIES INC