Non-volatile memory error correction

Abstract

Improving the performance, life and amount of data storage in write limited non-volatile memory may be achieved by: a) utilizing a serial content-addressable memory (CAM) to perform logical address translation, b) a minimum CAM function to perform erase error count wear leveling, c) increasingly refining a two dimensional error-correction coding (ECC) method as needed to correct for degrading storage, and / or d) serially generating ECC and using an ECC serial decoder to correct the data.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a continuation of U.S. patent application Ser. No. 13 / 659,368, filed on Oct. 24, 2012, which is incorporated by reference herein. This application is also related to U.S. patent application Ser. No. 13 / ______, filed on November xx, 2012, having the same title as the present application, corresponding to Attorney Docket No. 30003-00009-US1, and also incorporated herein by reference.FIELD OF THE INVENTION[0002]Flash and / or Phase Change Memories tend to fail after a limited number of write cycles. Embodiments of the present invention may pertain to minimizing and correcting read errors in such non-volatile storage. More specifically, such embodiments may pertain to a combination of techniques, such as modified wear leveling, varying orthogonal error correction with defect levels, and / or logical to physical address mapping utilizing a serial Content Addressable Memory (CAM).BACKGROUND OF THE INVENTION[0003]Non-volatile (NV...

AI Technical Summary

Benefits of technology

This patent aims to improve the accuracy and durability of NV memory by minimizing data errors and increasing error correction capabilities. This can help to extend the life and usage of NV memory.

Problems solved by technology

Non-volatile (NV) memories, such as electrically erasable programmable read only memories (EEPROMs) or NOR and NAND Flash memories typically have limited write cycles before failing, and may exhibit adjacent bit failures after too many read cycles.

Still, block erasures and page or word writes, where blocks may be much larger than the pages or words, may fail after a number of cycles.

As the non-volatile memory wears out, the errors increase.

Individual pages may fail on write or read cycles, and whole blocks may fail on erasure.

These failures may constitute an accumulation of individual bit failures after any given operation.

As the number of these bit failures increase, ECC may no longer correct them.

In some systems these pages or blocks may be marked bad and removed from the available storage.

In such systems, the memory capacity appears to reduce as the NV memory begins to wear out.

Some NV memory systems begin with failures, which may be marked as bad blocks or pages before being used.

It is known that these errors increase gradually, and eventually make the blocks and pages unusable, and it is also known that while errors increase with use, they may otherwise be very random.

And yet none of the current methods measure the actual errors or attempt to continue to use defective storage, beyond simple error correction.

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