Multi-Core Processor System

a processor system and multi-core technology, applied in the field of processor technologies, can solve the problems that the inter-core hardware message queue structure of the cmp in the prior art cannot meet the inter-core message exchange and task scheduling with higher performance, and achieve the effect of improving efficiency and performance of the multi-core processor system

Active Publication Date: 2014-08-14
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0010]As compared with the prior art, through the multi-core processor systems provided in various aspects of the present invention, the inter-core message exchange and task scheduling with higher performance can be satisfied, and the efficiency and performance of the multi-core processor systems are improved.

Problems solved by technology

However, inter-core hardware message queue structures of the CMP in the prior art cannot satisfy inter-core message exchange and task scheduling with higher performance.

Method used

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Embodiment Construction

[0012]An embodiment of the present invention provides a multi-core processor system. The system includes multiple central processor units and multiple groups of level-one hardware message queues, where each central processor unit is separately connected to a group of level-one hardware message queues and is configured to process messages in the level-one hardware message queues, where each group of level-one hardware message queues includes multiple level-one hardware message queues. In each group of level-one hardware message queues, a level-one hardware message queue having a higher priority is scheduled preferentially, and level-one hardware message queues having the same priority are scheduled in a round-robin manner according to round robin scheduling weights.

[0013]Another embodiment of the present invention further provides a multi-core processor system. The system includes multiple central processor units, multiple groups of level-one hardware message queues, and multiple gro...

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Abstract

The present invention provides a multi-core processor system, including: multiple central processor units and multiple groups of level-one hardware message queues. Each central processor unit is separately connected to a group of level-one hardware message queues and is configured to process messages in the level-one hardware message queues. Each group of level-one hardware message queues includes multiple level-one hardware message queues. Moreover, in each group of level-one hardware message queues, a level-one hardware message queue having a higher priority is scheduled preferentially, and level-one hardware message queues having the same priority are scheduled in a round-robin manner according to round robin scheduling weights. Through the multi-core processor system provided in the present invention, the efficiency and performance of the multi-core processor system are improved.

Description

[0001]This application is a continuation of International Application No. PCT / CN2012 / 070827, filed on Feb. 1, 2012, which is hereby incorporated by reference in its entirety.TECHNICAL FIELD[0002]The present invention relates to the field of processor technologies, and in particular, to a multi-core processor system.BACKGROUND[0003]Chip multi processors (CMP) refer to implementing multiple processor units (CPU) in one chip. Each CPU may also be called a core. The cores in the CMP share certain resources among each other and may execute different processes concurrently. Sometimes, procedures executed by the cores of the CMP need to share and synchronize data among each other, so the hardware structure of the CMP must support inter-core communications. Currently, there are two types of mainstream inter-core communication mechanisms. One type is a bus-shared cache structure. The other type is a hardware message queue structure.[0004]The bus-shared cache structure refers to that each cor...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F9/54
CPCG06F9/546G06F2209/548
Inventor ZHANG, WEIGUOWU, LIBO
Owner HUAWEI TECH CO LTD
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