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Substrate electroplating jig

a substrate electroplating and jig technology, applied in the field of substrate electroplating jigs, can solve the problems of low plating efficiency, time-consuming replacement of the conducting pin and the conducting member, and time-consuming replacement of the conducting pin and the conducting member, and achieve the effect of replacing the sealing packing

Inactive Publication Date: 2014-09-11
JCU CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The substrate plating jig can protect the conducting member from exposure to the plating solution, which ensures the electricity can be conducted to the substrate effectively. It is also easy to replace the seal packing when plating different types of substrates such as semiconductor wafers, glass plates, or ceramic plates.

Problems solved by technology

However, since the conducting pin of the plating jig of the related art is exposed to the plating solution, plating is precipitated also on the conducting pin, and hence plating efficiency is low and replacement of the conducting pin requires time.
Although these technologies can suppress exposure of the conducting pin and the conducting member to the plating solution, they have problems that the conducting pin and the conducting member are not configured to reliably come into contact with the semiconductor wafer for conducting electricity, replacement of the conducting pin and the conducting member requires time because of being too small in size, and replacement of the seal packing also requires time.

Method used

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  • Substrate electroplating jig
  • Substrate electroplating jig
  • Substrate electroplating jig

Examples

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Embodiment Construction

[0020]Hereinafter, a description of the present invention will be continued by reference to drawings illustrating a mode of the invention.

[0021]FIG. 1 is a perspective view of an entire substrate plating jig configured to hold a circular semiconductor wafer. In the drawing, reference numeral 1 denotes a substrate plating jig, 2 denotes a first holding member, 3 denotes a second holding member, 4 denotes a ring-shaped seal packing, 5 denotes a first ring-shaped conducting member having multiple protruding contact points, 6 denotes an opening, 7 denotes a second conducting member, 8 denotes a substrate base, 9 denotes a semiconductor wafer, 10 denotes a grip, and 11 denotes a hinge mechanism.

[0022]The substrate base 8 having substantially the same shape as the semiconductor wafer 9 is provided on an upper surface of the first holding member 2. Although the height of the substrate base 8 is not specifically limited, a height sufficient for providing a space which accommodates parts suc...

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Abstract

A substrate plating jig including a first plate-shaped holding member and a second holding member including a ring-shaped seal packing, including an internal circumferential part, an external circumferential part, and an opening formed at the center of the ring-shaped seal packing. Leading edges of the internal circumferential part and external circumferential part of the ring-shaped seal packing come in close contact with a substrate surface-to-be plated and the first holding member, respectively. The edge of the substrate-to-be-plated is held between the internal circumferential part and the external circumferential part of the ring-shaped seal packing. The substrate surface-to-be-plated is exposed in the opening. A first ring-shaped conducting member includes multiple protruding contact points inside the ring-shaped seal packing, and the substrate surface-to-be-plated comes in contact with the protruding contact points inside the ring-shaped seal packing by interposing and clamping the substrate-to-be-plated between the first holding member and the second holding member.

Description

TECHNICAL FIELD[0001]The present invention relates to a plating jig for holding a substrate when performing electrolytic plating on the substrate.BACKGROUND ART[0002]When applying electrolytic plating on substrates such as semiconductor wafers, glass plates, or ceramic plates, a plating jig that holds the substrate is configured to cause a conducting pin to come into contact with a conductive film on the substrate in a state of holding the substrate. Subsequently, in a state of holding the substrate with the plating jig, the substrate is immersed in electrolytic plating solution in a plating solution bath together with the jig, and electric current is passed from the conducting pin, so that the electrolytic plating is achieved.[0003]However, since the conducting pin of the plating jig of the related art is exposed to the plating solution, plating is precipitated also on the conducting pin, and hence plating efficiency is low and replacement of the conducting pin requires time.[0004]...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): C25D17/06
CPCC25D17/06C25D7/123C25D17/001C25D17/004C25D17/005
Inventor YOSHIOKA, JUNICHIROMURAYAMA, TAKASHI
Owner JCU CORP
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