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Local Evaluation Circuit for Static Random-Access Memory

a random-access memory and local evaluation technology, applied in the field of static random-access memory, can solve problems such as data eventually losing

Inactive Publication Date: 2014-09-11
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent describes a circuit for evaluating a memory array which includes two NAND gates and their associated local and global bit lines. The circuit allows for faster evaluation of different columns of memory cells in the array. The technical effects of this invention include increased speed and efficiency in evaluating memory arrays.

Problems solved by technology

SRAM exhibits data remanence, but is still volatile in the conventional sense that data is eventually lost when the SRAM is not powered.

Method used

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  • Local Evaluation Circuit for Static Random-Access Memory
  • Local Evaluation Circuit for Static Random-Access Memory
  • Local Evaluation Circuit for Static Random-Access Memory

Examples

Experimental program
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Embodiment Construction

[0020]The illustrative embodiments provide an evaluation circuit for a static random-access memory (SRAM).

[0021]In the following detailed description of exemplary embodiments of the invention, specific exemplary embodiments in which the invention may be practiced are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, architectural, programmatic, mechanical, electrical and other changes may be made without departing from the spirit or scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims and equivalents thereof.

[0022]It is understood that the use of specific component, device, and / or parameter names are for example only and not meant to imply any limitations on the invention. The invention may thus be implemented with differ...

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Abstract

A local evaluation circuit for a memory array includes first and second NAND gates and first, second, third, and fourth switches. The first switch is configured to couple a first node of the second NAND gate to a first power supply node in response to a first read signal. The second switch is configured to couple a first node of the first NAND gate to the first power supply node in response to a second read signal. The third switch is configured to couple a second node of the first NAND gate to a second power supply node in response to the first read signal. The fourth switch is configured to couple a second node of the second NAND gate to the second power supply node in response to the second read signal.

Description

BACKGROUND[0001]The disclosure generally relates to static random-access memory and, in particular, a local evaluation circuit for a static random-access memory.[0002]Static random-access memory (SRAM) is a type of semiconductor memory that uses bistable latching circuitry to store each bit. The term static differentiates SRAM from dynamic random-access memory (DRAM), which must be periodically refreshed. SRAM exhibits data remanence, but is still volatile in the conventional sense that data is eventually lost when the SRAM is not powered. Typically, each bit in an SRAM is stored on four transistors that form a storage cell having two cross-coupled inverters. The storage cell has two stable states that are denoted ‘0’ and ‘1’. Usually, two additional access transistors serve to control access to the storage cell during read and / or write operations. In general, an SRAM utilizes six metal-oxide semiconductor field-effect transistors (MOSFETs) to store each memory bit. Other types of S...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G11C7/12G11C7/00
CPCG11C7/12G11C7/00G11C7/1051G11C7/18G11C11/418G11C11/419G11C11/4096G11C7/10
Inventor CHAN, YUEN HUNGKUGEL, MICHAELPENTH, SILKEWERNER, TOBIAS
Owner IBM CORP