Microelectronic element with bond elements to encapsulation surface

Abstract

A microelectronic structure includes a semiconductor having conductive elements at a first surface. Wire bonds have bases joined to the conductive elements and free ends remote from the bases, the free ends being remote from the substrate and the bases and including end surfaces. The wire bonds define edge surfaces between the bases and end surfaces thereof. A compliant material layer extends along the edge surfaces within first portions of the wire bonds at least adjacent the bases thereof and fills spaces between the first portions of the wire bonds such that the first portions of the wire bonds are separated from one another by the compliant material layer. Second portions of the wire bonds are defined by the end surfaces and portions of the edge surfaces adjacent the end surfaces that are extend from a third surface of the compliant later.

Description

BACKGROUND OF THE INVENTION[0001]The subject matter of the present application relates to a microelectronic element including a semiconductor chip with structures to achieve improved reliability when assembled with external microelectronic components, including compliant connection structures, and methods of fabricating the microelectronic element.[0002]Semiconductor chips are flat bodies with contacts disposed on a front surface that are connected to internal electrical circuitry of the chip. The chips are typically packaged to form a microelectronic package having terminals that are electrically connected to the chip contacts. The terminals of the package may then be connected to an external microelectronic component, such as a circuit panel.[0003]Microelectronic devices such as semiconductor chips typically require many input and output connections to other electronic components. The input and output contacts of a semiconductor chip or other comparable device are generally dispos...

AI Technical Summary

Benefits of technology

The present patent relates to a microelectronic structure and package that includes a semiconductor die with wire bonds and a compliant material layer. The wire bonds are positioned between the semiconductor die and external conductive features, and the compliant material layer fills the spaces between the wire bonds and the substrate. The compliant material layer has a third surface facing away from the substrate, and second portions of the wire bonds are defined by the end surfaces of the wire bonds. The technical effect of this patent is to provide a more robust and reliable connection between the semiconductor die and external conductive features, while also improving the overall performance and reliability of the microelectronic package.

Problems solved by technology

Mismatches or differences between coefficients of thermal expansion (“CTE”) of the components in such a package can adversely impact their reliability and performance.

This can cause stress in the solder masses (or other structures) used to both mount and electrically connect the semiconductor die and the substrate.

Such stress can cause the solder mass to disconnect from either or both of the semiconductor die or the substrate, thereby interrupting the signal transmission that it otherwise facilitates.

Various structures have been used to compensate for such variations in CTE, yet many fail to offer a significant amount of compensation on a scale appropriate for the fine pitch arrays being increasingly utilized in microelectronic packages.

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