Control circuit for bit-line sense amplifier and semiconductor memory apparatus having the same, and operating method thereof

Abstract

A control circuit for a bit-line sense amplifier may include: a bank active signal generator configured to generate an internal active signal and a bank active signal; and a sense amplifier enable signal generator configured to determine a skew in response to the internal active signal, and set an output time of a sense amplifier enable signal by delaying the bank active signal according to the determined skew.

Description

CROSS-REFERENCES TO RELATED APPLICATION[0001]The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2013-0147763, filed on Nov. 29, 2013, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.BACKGROUND[0002]1. Technical Field[0003]Various embodiments relate to a semiconductor integrated circuit, and more particularly, to a control circuit for a bit-line sense amplifier (BLSA), a semiconductor memory apparatus having the same, and an operating method thereof.[0004]2. Related Art[0005]A semiconductor memory apparatus, or particularly, DRAM uses a bit-line sense amplifier to sufficiently amplify charge stored in a memory cell, when reading information of the memory cell.[0006]Referring to FIG. 1, the control circuit 10 for a bit-line sense amplifier may include a bank active signal generator 101, a sense amplifier enable signal generator 103, a control signal generator 105, and a sense amplifier d...

AI Technical Summary

Benefits of technology

This adaptive approach ensures consistent charge sharing times across high-speed and low-speed environments, reducing the likelihood of failures and optimizing operating efficiency by dynamically adjusting the sense amplifier enable signal timing.

Problems solved by technology

Also, when the time tRCD is shortened, the charge sharing time may be reduced, and charge sharing may not be sufficiently performed.

Then, a fail may occur in the bit line sense amplifier.

However, the fabrication environment and operation environment of the semiconductor memory apparatus are variable, a fail is still likely to occur during a read operation based the fixed time tRCD, and an unnecessary operation time may be required.

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