Semiconductor Device Package and Method of the Same

Abstract

The invention proposes a semiconductor device package structure, comprising a substrate, an adhesive layer and a die. The substrate has electrical through-holes to inter-connect a first and second wiring circuit on a top surface and a bottom surface of the substrate respectively, wherein a contact conductive bump is formed on the first wiring circuit. The under-fill adhesive layer is formed on the top surface and the first wiring circuit of the substrate except the area of the die. The die has a bump structure on the bonding pads of the die, wherein the bump structure of the die is electrically connected to the contact conductive bump of the first wiring circuit of the substrate.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application is a Divisional of co-pending application Ser. No. 14 / 223,157, filed on Mar. 24, 2014, for which priority is claimed under 35 U.S.C. §120, the entire contents of which are hereby incorporated by reference.TECHNICAL FIELD[0002]The invention relates to a semiconductor device package, and more particularly to a semiconductor device package with dual substrates having die embedded therein.BACKGROUND[0003]In the field of semiconductor devices, the device density is increased and the device dimension is reduced, continuously. The demand for the packaging or interconnecting techniques in such high density devices is also increased to fit the situation mentioned above. Conventionally, in the flip-chip attachment method, an array of solder bumps is formed on the surface of the die after the re-distribution layer be formed. The formation of the solder bumps may be carried out by using a solder composite material through a solder mas...

AI Technical Summary

Benefits of technology

The patent is about a new type of semiconductor chip package that uses two substrates with window openings for dies. This improves reliability and reduces device size. The chip also has lower and upper wiring patterns that increase electrical conductivity, made through copper clad laminate and metal plating. Overall, the patent aims to provide more efficient and reliable semiconductor chips with improved performance.

Problems solved by technology

As a semiconductor become more complicated, the traditional package technique, for example lead frame package, flex package, rigid package technique, can't meet the demand of producing smaller chip with high density elements on the chip.

In a large number of image sensors, a photodiode structure called a pinned or a buried photodiode is used because of its low noise performance.

Although these methods eliminate the difficulties associated with wire bonding, however, the PCB's is very large with respect to the size of the image sensor chip and the transparent cover.

Moreover, the conductive film risks interference with sensing circuitry on the image sensor chip and requires the formation of dummy leads or dam structures to compensate for this problem.

Thus, the thickness of the substrate is unlikely to be scaled down due to the structure has ball high and extruding die receiving structure which limits the scale of the package shrinkage.

The prior arts suffer complicated processes to form the image package and the package structure is unable to be scaled down.

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