3D stacked IC device with stepped substack interlayer connectors

Abstract

A stepped substack interlayer connector structure on a multilayer integrated circuit includes N steps on the substrate from a surface of the substrate at a first level to a surface of the substrate at a second level. A stack of active layers alternating with insulating layers on the substrate, including a plurality of substacks disposed in relation to the N step(s) to form respective contact regions in which the substacks are disposed at a common level. Interlayer connectors are formed by conductors in the respective regions connected to landing areas on active layers in each of the plurality of substacks. The maximum depth of the interlayer connectors is equal to, or less than, the thickness of one of the substacks.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to interlayer connectors for multi-layer integrated circuits and the like, including high density three-dimensional (3D) memory devices.[0003]2. Description of Related Art[0004]In the manufacturing of high density memory devices, the amount of data per unit area on an integrated circuit can be a critical factor. Thus, as the critical dimensions of the memory devices approach lithographic technology limits, techniques for stacking multiple levels or layers of memory cells have been proposed in order to achieve greater storage density and lower costs per bit.[0005]For example, thin film transistor techniques are applied to charge trapping memory in Lai, et al., “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006; and in Jung et al., “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crys...

AI Technical Summary

Problems solved by technology

The cost to implement the interconnections increases with the number of lithographic steps needed.

However, limitations can arise as the number of layers increases, because not only does the number of etch steps increase even using binary system etch approaches, but also the depths of the required vias increase.

With greater depths, the layout area for each interlayer connector can increase and process control issues arise.

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