Clock data recovery circuit and semiconductor device

Abstract

A clock data recovery circuit is configured to receive an input data signal formed of a series of input data pieces synchronized with a reference clock signal, and to generate a regenerated clock signal. The clock data recovery circuit includes a regenerated clock generating circuit; a latch circuit; a comparison circuit; a logical sum signal generating circuit; and a charge pump.

Description

BACKGROUND OF THE INVENTION AND RELATED ART STATEMENT[0001]The present invention relates to a clock data recovery circuit, a phase synchronization circuit, and a semiconductor device having the clock data recovery circuit.[0002]As a current communication method of high speed serial data, an embedded clock method, in which a clock signal is overlapped with a data signal and is transmitted, has been adopted. When the embedded method is adopted to a reception device of a communication system, the reception device may include a conventional clock data recovery circuit for regenerating the clock signal from the data signal thus received using a synchronization of data transition in the data signal thus received, and for retrieving the data signal thus received at a timing of the clock signal thus regenerated.[0003]Patent Reference has disclosed an example of the conventional clock data recovery circuit. According to Patent Reference, the conventional clock data recovery circuit may be fo...

AI Technical Summary

Benefits of technology

This solution enhances the ability of the clock to follow data transitions while minimizing jitter, thereby improving data transmission efficiency and extending the period when data is not transitioning, without significant increases in jitter or frequency adjustments.

Problems solved by technology

Accordingly, unless the input data is transited, the phase comparison is not performed, so that it is difficult to maintain the synchronization.

In this case, when it is tried to shorten a time of period when the data is not transited, it is necessary to insert the dummy bit at a higher frequency, thereby deteriorating efficiency of data transfer.

In the conventional clock data recovery circuit disclosed in Patent Reference, when the charge pump charges a small amount of the electron charge amount, it is difficult for the clock to follow the pattern change of the data when the charge pump voltage to be supplied to the VCO is changed according to the comparison result of the phase comparison circuit.

As a result, it is difficult to synchronize the data with the clock.

On the other hand, when the charge pump charges a large amount of the electron charge amount, it is become too sensitive relative to even a slight phase change.

As a result, the frequency of the VCO is excessively changed, thereby increasing jitter of the clock.

Accordingly, a margin of setting up and holding of the FFs of the latch circuit, thereby making it difficult to accurately retrieve the data.

Accordingly, it is difficult to prolong a period of time when the data is not transited.

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