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Atomic memory operations on an n-way linked list

Inactive Publication Date: 2016-06-30
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent text describes a computer-implemented method for pushing and popping elements onto an N-way linked list in a computer memory. The method allows multiple threads to concurrently push and pop elements onto the list, ensuring that no thread corrupts the list. The method uses a handle that identifies the location of the tail element of the list and a parameter that tracks the number of elements in the list. The method includes a push method for pushing elements onto the list and a pop method for popping elements off the list. The technical effects of the method include higher rates of element pushing and popping, improved efficiency, and better performance in computer memory.

Problems solved by technology

However, SIMD instructions may not be suitable for use with known algorithms and data structures.
During runtime, if a program does not use all of the memory allocated for the array, memory is wasted.
On the other hand, if the program needs a larger array at runtime than the predefined size, it's generally inefficient to expand the size of the array.

Method used

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  • Atomic memory operations on an n-way linked list
  • Atomic memory operations on an n-way linked list
  • Atomic memory operations on an n-way linked list

Examples

Experimental program
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Embodiment Construction

[0038]A variety of examples are presented in this Detailed Description. These examples may be referred to as exemplary. Note that the term “exemplary,” as used in this Detailed Description, simply means an example, instance, or illustration. This term is not used to mean that a particular example is superior, commendable, or otherwise deserving of imitation over other examples.

[0039]Accessing an N-Way Linked List

[0040]An N-way linked list according to various embodiments includes elements for storing data, two or more sub-lists, and a handle. The handle may include tail elements, head elements, or both for each of the sub-lists. The handle may be an array of handles for individual sub-lists. In addition, parameters that track the number of elements added or removed from the various sub-lists may be associated with an N-way linked list. Exemplary “ITAIL” and “RTAIL” parameters for tracking the addition and removal of elements are described below.

[0041]Referring to FIGS. 1A-1C, an ele...

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Abstract

Computer-implemented methods for pushing or popping an element on to of off of an N-way linked list in a computer memory may include one or more atomic memory operations on a handle of the N-way linked list. One embodiment for pushing a first element on to an N-way linked list may include setting a next sequential element pointer of the first element to point to an unknown location marker. Another embodiment for popping a first element off of an N-way linked may include marking a sub-list tail handle with a designation indicating that the particular sub-list is involved in a pop process. In yet another embodiment, a method for popping a first element off of an N-way linked list may include storing in a sub-list tail handle a pointer to a pseudo element. The handle may fit within a single line of cache memory.

Description

BACKGROUND[0001]This disclosure relates generally to data structures stored in computer memory, and more particularly, to accessing elements in data structures stored in computer memory.[0002]Some currently available processors support single instruction, multiple data (SIMD) operations. A SIMD operation is an operation in which a single instruction operates on two or more data elements items in parallel. For example, a SIMD load instruction may load eight 16-bit values in parallel. In this example, in the same number of clock cycles needed to perform a conventional load instruction that loads a single 16-bit value, a SIMD load instruction would load eight 16-bit values. SIMD processing may be referred to as vector processing. SIMD instructions provide a significant speed up over comparable conventional instructions. However, SIMD instructions may not be suitable for use with known algorithms and data structures. One example processor that supports SIMD instructions is the Pentium® ...

Claims

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Application Information

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IPC IPC(8): G06F12/12
CPCG06F9/30043G06F9/50G06F12/0875G06F2209/521G06F9/52
Inventor STEINMACHER-BUROW, BURKHARD
Owner IBM CORP
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