Three-dimensional semiconductor memory device and method of fabricating the same

a semiconductor memory and three-dimensional technology, applied in the field of three-dimensional (3d) semiconductor memory devices, can solve the problems of high cost of equipment that forms minute patterns, high cost of semiconductor devices, and manufacturing obstacles in achieving low-cost, mass-production 3d semiconductor memory devices

Inactive Publication Date: 2016-09-22
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0022]In an exemplary embodiment of the inventive concept, a first circumference of the first channel pattern decreases in a direction toward the substrate, and a second circumference of the second channel pattern decreases in the direction toward the substrate.

Problems solved by technology

The degree of integration of a semiconductor device is a factor of the cost of such device.
However, the cost of equipment that forms minute patterns is high.
However, manufacturing obstacles are encountered in achieving low-cost, mass-production 3D semiconductor memory devices.
The manufacturing obstacles may affect the reliability of such devices.

Method used

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  • Three-dimensional semiconductor memory device and method of fabricating the same
  • Three-dimensional semiconductor memory device and method of fabricating the same
  • Three-dimensional semiconductor memory device and method of fabricating the same

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Embodiment Construction

[0051]Exemplary embodiments of the inventive concepts will be described more fully hereinafter with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments thereof set forth herein. The exemplary embodiments of the inventive concept disclosed herein are provided to convey the inventive concept to those of ordinary skill in the art. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity. Like reference numerals in the drawings may denote like elements throughout the specification. Thus a duplicate description thereof may be omitted.

[0052]It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. As used herein the term “and / or” includes any and all combinations of one or more of the a...

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Abstract

A semiconductor memory device includes a stack including gate electrodes sequentially stacked on a substrate, a vertical insulating structure penetrating the stack vertically with respect to the gate electrodes, a vertical channel portion disposed on an inner side surface of the vertical insulating structure, and a common source region formed in the substrate and spaced apart from the vertical channel portion. A bottom region of the vertical channel portion has a protruding surface in contact with a bottom region of the vertical insulating structure.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2015-0036839, filed on Mar. 17, 2015, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein.TECHNICAL FIELD[0002]Exemplary embodiments of the inventive concept relate to a semiconductor device and a method of fabricating the same, and in particular, to a three-dimensional (3D) semiconductor memory device and a method of fabricating the same.DISCUSSION OF THE RELATED ART[0003]The degree of integration of a semiconductor device is a factor of the cost of such device. In the case of two-dimensional (2D) or planar semiconductor memory devices, since their integration is determined by the area occupied by a unit memory cell, integration depends on how small the patterns of the semiconductor can be formed. However, the cost of equipment that forms minute patterns is high.[0004]Thr...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L27/115H01L29/10
CPCH01L29/1037H01L27/11582H10B43/35H10B43/10H10B43/27
Inventor CHOI, JI-HOONLIM, SEUNGHYUNKIM, SUNGGILKIM, HONGSUKLIM, HUNHYEONGSIM, HYUNJUN
Owner SAMSUNG ELECTRONICS CO LTD
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