3D voltage switching transistors for 3D vertical gate memory array

Abstract

The area consumed by switching transistors for a 3D NAND memory array can be reduced with 3D voltage switching transistors with reduced aggregate area in comparison with 2D voltage switching transistors such as transistors in the substrate. The integrated circuit comprises a 3D NAND array of memory transistors; a plurality of bit lines, with different ones of the plurality of bit lines electrically coupled to different parts of the 3D NAND array; and a plurality of transistor pairs with a stack of semiconductor layers. Different layers in the stack of semiconductor layers include different transistor pairs of the plurality of transistor pairs. Each of the plurality of transistor pairs includes first and second transistors with first, second, and third source / drain terminals. The first transistor includes the first and the third source / drain terminals, and the second transistor includes the second and the third source / drain terminals. The first source / drain terminal is electrically coupled to an erase voltage line. The second source / drain terminal is electrically coupled to a corresponding one of a plurality of program / read voltage lines. The third source / drain terminal is electrically coupled to a corresponding one of the plurality of bit lines.

Description

BACKGROUND OF THE INVENTION[0001]NAND memory arrays use high voltage switching transistors to isolate the erase voltage from the array and from sense amplifiers. Although both read and program operations use relatively low voltages, an erase operation couples a high magnitude voltage to the array. Thus high voltage switching transistors electrically decouple the array from the sensing circuits to avoid junction breakdown.[0002]Commonly, during the erase operation of a 2D NAND memory array, the potential is raised in the PWI region, the uppermost p-type region in a triple well. One typical 2D NAND memory array arrangement uses a group of 4 high voltage switching MOSFETs positioned outside of the PWI region to electrically decouple the array from the erase voltage.[0003]In another 2D NAND memory array arrangement the PWI region is shared by the memory array and the 4 switching MOSFETs to prevent large voltage differences and allow the use of low voltage design rules for the 4 switchin...

AI Technical Summary

Benefits of technology

This patent technology reduces the space taken up by switches in a 3D NAND memory array. By using a vertical gate memory configuration, 3D voltage switching transistors are designed to have less aggregate area than 2D transistors in the substrate. This allows for a more efficient use of space in the memory array, improving overall performance and reliability.

Problems solved by technology

As a result, in 3D NAND memory architecture, the high voltage switching transistors lines consume a significant amount of area.

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