Multilayer semiconductor integrated circuit device
a semiconductor integrated circuit and multi-layer technology, applied in semiconductor devices, semiconductor/solid-state device details, electrical apparatus, etc., can solve the problems of increasing mounting volume, limit in and wire bonding, so as to reduce the number of bonding wires and reduce the number of wires. , the effect of reducing the number of wires
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example 1
[0086]Next, the multilayer semiconductor integrated circuit device according to Example 1 of the present invention is described in reference to FIGS. 5A through 10K as an example where three memory chips that are the same are layered on top of each other. As illustrated in FIG. 5A, first, B ions with a dosage of 1×1016 cm−2 are implanted into a p− type Si substrate 21 with an energy for acceleration of 200 keV so as to form a p++ type well region 22 having a size of 0.1 mm×7 mm, and then, P ions with a dosage of 1×1016 cm−2 are implanted into the p− type Si substrate 21 with an energy for acceleration of 200 keV so as to form an n++ type well region 23 having a size of 0.1 mm×7 mm. Next, heat treatment is carried out for 50 hours at 1,050° C. so that the implanted ions are activated, and at the same time are diffused deeper in the direction of the thickness of the substrate. Here, the oxide film formed on the surface of the substrate as a result of heat treatment is removed if neces...
example 2
[0097]Next, the multilayer semiconductor integrated circuit device according to Example 2 of the present invention is described in reference to FIG. 11, which illustrates only the final structure because the basic manufacturing process and the basic structure are the same as in Example 1. FIG. 11 is a schematic cross-sectional diagram illustrating the multilayer semiconductor integrated circuit device according to Example 2 of the present invention, wherein a high impurity well region is not formed in the semiconductor integrated circuit device in the final tier (the third tier at the bottom in the figure), and the rest of the configuration is the same as in Example 1.
[0098]Thus, it is not necessary for the chip in the final stage to convey the power supply to the next tier, and therefore, a high impurity well region is not necessary. Accordingly, in the case where chips having different properties are layered on top of each other, the arrangement of a particular chip in the final t...
example 3
[0099]Next, the multilayer semiconductor integrated circuit device according to Example 3 of the present invention is described in reference to FIG. 12, which illustrates only the final structure because the basic manufacturing process and the basic structure are the same as in Example 1. FIG. 12 is a schematic cross-sectional diagram illustrating the multilayer semiconductor integrated circuit device according to Example 3 of the present invention, wherein micro-bumps 66 are used for the connection between chips instead of ordinary temperature pressure applying connection, and the rest of the configuration is the same as in Example 1.
[0100]Thus, micro-bumps 66 are used for the connection between chips so that the connection between chips can further be made strong electrically and mechanically.
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