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Semiconductor device and device for a semiconductor device

a semiconductor memory device and semiconductor technology, applied in the direction of information storage, static storage, digital storage, etc., can solve the problems of inefficient discarding of the entire semiconductor memory device, only a few memory cells affected, etc., and achieve the effect of increasing the refresh ra

Active Publication Date: 2017-02-23
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent is for a device that can refresh a semiconductor device faster by activating multiple word lines simultaneously based on a single command. The device can also sequentially activate the word lines based on a repair detection signal. The technical effect of this patent is to improve the speed and efficiency of refreshing semiconductor devices.

Problems solved by technology

As the process technology of the semiconductor memory device advances, defects occur in only some memory cells.
It is very inefficient to discard the entire semiconductor memory device due to these failed memory cells when considering the yield of products.

Method used

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  • Semiconductor device and device for a semiconductor device
  • Semiconductor device and device for a semiconductor device
  • Semiconductor device and device for a semiconductor device

Examples

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Embodiment Construction

[0020]Hereinafter, a semiconductor device will be described below with reference to the accompanying drawings through various examples of embodiments.

[0021]In general, a redundancy circuit for such a repair operation may be included in each of a plurality of banks included in a semiconductor memory device. Each of the banks may include a cell mat configured to include a plurality of unit cells, a row control region configured to include circuits for controlling row access, and a column control region configured to include circuits for controlling column access.

[0022]The redundancy circuit may be divided into a row redundancy circuit for repairing the row address of a fail unit cell and a column redundancy circuit for repairing the column address of a fail unit cell. The row redundancy circuit and the column redundancy circuit may be respectively included in the row control region and column control region of each bank.

[0023]Various embodiments may be directed to a technology for ski...

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Abstract

Various embodiments generally relate to a semiconductor device and a device for a semiconductor device, and more particularly, to a technology relating to a margin of a data retention time. The semiconductor device may include a repair detection unit configured to determine whether an inputted address is a repair address and output a repair detection signal. The semiconductor device may include a refresh control unit configured to simultaneously activate two or more word lines in response to a refresh command signal and sequentially activate the two or more word lines according to the repair detection signal.

Description

CROSS-REFERENCES TO RELATED APPLICATION[0001]The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2015-0117929, filed on Aug. 21, 2015, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.BACKGROUND[0002]1. Technical Field[0003]Various embodiments generally relate to a semiconductor device and a device for a semiconductor device, and more particularly, to a technology relating to a margin of a data retention time.[0004]2. Related Art[0005]In general, a semiconductor memory device including double data rate synchronous DRAM (DDR SDRAM) includes a very large number of memory cells. The integration degree of semiconductor memory devices is increased according to the development of a process technology, and thus the number of memory cells is further increased. If any one of such memory cells fails, a semiconductor memory device including the fail memory cell must be discharged because it does no...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G11C29/00G11C11/408G11C11/406G11C11/4096
CPCG11C29/76G11C11/406G11C11/4085G11C11/4096G11C29/12G11C29/18G11C29/44G11C2229/74G11C2029/1202G11C2029/1802G11C8/08G11C11/4087
Inventor KIM, JAE ILBAEK, SEUNG GEUNCHOI, DON HYUN
Owner SK HYNIX INC