Stacked chip package structure and manufacturing method thereof

a technology of stacking and chip, applied in the direction of semiconductor devices, electrical devices, semiconductor/solid-state device details, etc., can solve the problems of disadvantageous damage to devices including semiconductor chips, and achieve the effects of reducing production costs, reducing production costs, and reducing overall thickness
US20170287870A1Inactive Publication Date: 2017-10-05POWERTECH TECHNOLOGY
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Patent Information

Authority / Receiving Office
US · United States
Current Assignee / Owner
POWERTECH TECHNOLOGY
Publication Date
2017-10-05
Estimated Expiration
Not applicable · inactive patent

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Abstract

A stacked chip package structure includes a first chip, stud bumps, a second chip, pillar bumps, an encapsulant and conductive vias. The first stud bumps are respectively disposed on a plurality of first pads of the first chip, wherein each first stud bump includes a rough surface, and the rough surface of each first stud bump is rougher than a top surface of each first pad. The second chip is disposed on the first chip and exposes the first pads. The pillar bumps are respectively disposed on a plurality of second pads of the second chips. The encapsulant encapsulates the first chip and the second chip and exposes a top surface of each second stud bump. The first conductive vias penetrate the encapsulant and connect the first stud bumps. Each first conductive via covers the rough surface of each first stud bump.
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Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] The application claims the priority benefit of U.S. provisional application Ser. No. 62 / 316,843, filed on Apr. 1, 2016 and Taiwan application serial no. 105137133, filed on Nov. 14, 2016. The entirety of each of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.BACKGROUND OF THE INVENTIONField of the Invention

[0002] The present invention generally relates to a chip package structure and a manufacturing method thereof. More particularly, the present invention relates to a stacked chip package structure and a manufacturing method thereof.Description of Related Art

[0003] Recently, attention has paid to a semiconductor device called a “substrate with a built-in chip” in which a chip and the like are embed in a substrate made of resin and the like and a semiconductor device in which an insulating layer and a wiring layer are formed on the chip. In semiconductor devices such as ...

Claims

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