Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Finfet with improved gate dielectric

a gate dielectric and gate dielectric technology, applied in the field of semiconductor device structure, can solve the problems of time-dependent dielectric breakdown, negative bias temperature instability and positive bias temperature instability improve the integrity of the gate dielectric, and improve the reliability of the finfet devi

Inactive Publication Date: 2018-05-24
SEMICON MFG INT (SHANGHAI) CORP +1
View PDF6 Cites 1 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present patent text describes a method for improving the reliability and performance of fin-type semiconductor devices. The method involves introducing fluorine ions into the top portion of the fin through a process of ion implantation. This results in an improvement in various reliability tests such as gate dielectric integrity, time-dependent dielectric breakdown, negative bias temperature instability, and positive bias temperature instability of the FinFET device. Overall, this method provides a way to manufacture fin-type semiconductor devices with better reliability and performance.

Problems solved by technology

The novel method of introducing fluorine ions into the fin of a FinFET device results in an improvement in gate dielectric integrity, time-dependent dielectric breakdown, negative bias temperature instability and positive bias temperature instability of the FinFET device.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Finfet with improved gate dielectric
  • Finfet with improved gate dielectric
  • Finfet with improved gate dielectric

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0037]In the following description, numerous specific details are provided for a thorough understanding of the present invention. However, it should be appreciated by those of skill in the art that the present invention may be realized without one or more of these details. In other examples, features and techniques known in the art will not be described for purposes of brevity.

[0038]It should be understood that the drawings are not drawn to scale, and similar reference numbers are used for representing similar elements. Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. The thickness of layers and regions in the drawings may be exaggerated relative to each other for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, e...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A semiconductor device includes a substrate structure comprising a substrate and a plurality of fins on the substrate. Each of the fins includes a fluorine-doped top portion.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS[0001]This application is a divisional of U.S. application Ser. No. 15 / 236,331, filed on Aug. 12, 2016, which claims priority to Chinese patent application No. 201610018952.5, filed on Jan. 13, 2016, the content of which is incorporated herein by reference in its entirety.BACKGROUND OF THE INVENTION[0002]The present invention relates generally to semiconductor technology. Specifically, embodiments of the invention are directed to semiconductor device structures and a method of manufacturing the same.[0003]As the feature size of metal oxide semiconductor field-effect transistors (MOSFETs) continues to decrease, short channel effects have become a critical design issue due to the reduction in the size of the gate length. Fin Field-effect transistor (FinFET) devices exhibit excellent gate controllability on channel charge, superior electrostatic control capability, higher drive current and lower power consumption, so that the feature size of comp...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(United States)
IPC IPC(8): H01L29/66H01L29/78H01L21/306H01L21/265H01L29/06H01L29/36H01L21/308
CPCH01L29/7851H01L29/785H01L21/30604H01L21/30625H01L21/265H01L29/0649H01L29/36H01L29/66795H01L21/3085H01L21/26506H01L21/823431H01L27/0886H01L29/66803
Inventor LI, YONG
Owner SEMICON MFG INT (SHANGHAI) CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com