Method for preparing a semiconductor package
a semiconductor and package technology, applied in the field of semiconductor package preparation, can solve the problems of poor electrical interconnection, complexity of manufacturing semiconductor devices, and increasing complexity of semiconductor devices, and achieve the effect of reducing the fabrication cost of semiconductor packages
Inactive Publication Date: 2018-07-19
NAN YA TECH
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- Description
- Claims
- Application Information
AI Technical Summary
Benefits of technology
The lateral bump structure effectively establishes signal paths between semiconductor devices without redistribution structures, meeting miniaturized scale demands and reducing fabrication costs by simplifying the manufacturing process.
Problems solved by technology
Accordingly, the manufacturing of semiconductor devices in a miniaturized scale is becoming more complicated.
An increase in the complexity of manufacturing semiconductor devices may cause deficiencies such as poor electrical interconnection, development of cracks, or delamination of components.
As such, there are many challenges to be overcome when modifying the structure and manufacture of semiconductor devices.
Method used
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[0038]The following description of the disclosure accompanies drawings, which are incorporated in and constitute a part of this specification, and which illustrate embodiments of the disclosure, but the disclosure is not limited to the embodiments. In addition, the following embodiments can be properly integrated to complete another embodiment.
[0039]References to “one embodiment,”“an embodiment,”“exemplary embodiment,”“other embodiments,”“another embodiment,” etc. indicate that the embodiment(s) of the disclosure so described may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Further, repeated use of the phrase “in the embodiment” does not necessarily refer to the same embodiment, although it may.
[0040]The present disclosure is directed to a semiconductor package having a lateral bump structure implementing a lateral signal path between two laterally adjacent devices and ...
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The present disclosure provides a method far preparing a semiconductor package. The semiconductor package includes a semiconductor device having an upper surface and a side, wherein the upper surface and the side form a corner of the semiconductor device. The semiconductor package also includes a lateral bump structure disposed on the side and implementing a lateral signal path of the semiconductor device. The semiconductor package further includes a vertical hump structure disposed over the upper surface and implementing a vertical signal path of the semiconductor device.
Description
PRIORITY CLAIM AND CROSS-REFERENCE[0001]This patent application is a divisional application of and claims priority to U.S. patent application Ser. No. 15 / 410,246, filed on Jan. 19, 2017, which is incorporated by reference in its entirety.TECHNICAL FIELD[0002]The present disclosure relates to a semiconductor package and to a method for preparing the same, and particularly relates to a semiconductor package having a lateral bump structure implementing a lateral signal path between two laterally adjacent devices and a method for preparing the same.DISCUSSION OF THE BACKGROUND[0003]Semiconductor devices are essential for many modern applications. With the advancement of electronic technology, semiconductor devices are becoming smaller in size while having greater functionality and greater amounts of integrated circuitry. Due to the miniaturized scale of semiconductor devices, chip-on-chip technique is now widely used for manufacturing semiconductor devices. Numerous manufacturing steps ...
Claims
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IPC IPC(8): H01L23/00H01L23/31H01L21/56
CPCH01L2224/11849H01L2224/1132H01L2224/16137H01L2224/1418H01L2224/13026H01L24/14H01L24/11H01L23/3114H01L24/16H01L24/13H01L21/565H01L21/56H01L23/31H01L2924/15192H01L25/0655H01L2225/06551H01L2224/24137H01L2224/04105H01L2224/12105H01L2924/18162H01L2224/1403H01L2224/0401H01L2224/05568H01L2224/05569H01L2224/0603H01L2224/06183H01L2224/94H01L24/03H01L24/05H01L2224/81815H01L2224/05548H01L2224/1147H01L2224/81805H01L24/94H01L2224/14183H01L24/96H01L24/81H01L2224/05624H01L2224/13111H01L2224/05647H01L2224/131H01L2224/05655H01L2224/13147H01L2224/05611H01L2224/05644H01L2224/13139H01L2224/05639H01L2224/03H01L2224/11H01L2924/00014H01L2924/014H01L2924/01029H01L2924/01047H01L2924/0105H01L2924/01322
Inventor LIN, PO-CHUNCHU, CHIN-LUNG
Owner NAN YA TECH