Pipelined analog-to-digital converter and operating method thereof

Abstract

A pipelined analog-to-digital converter (ADC) and an operating method are provided. The pipelined ADC includes a multiplying digital-to-analog converter (MDAC) and a sub-ADC. The MDAC alternatively operates in an amplifying phase and a sampling phase according to two non-overlapping clocks, and performs operations on an input signal in the amplifying phase according to a target voltage determined by a digital code. The sub ADC includes multiple comparators, a determination circuit, and an encoding circuit. The comparators generate multiple comparison results by comparing the input signal with multiple predetermined voltages. The determination circuit generates multiple comparison completion signals in a non-overlapping interval of the two clocks according to the comparison results. The comparison completion signals respectively indicate whether the comparators complete the comparison. The encoding circuit determines the digital code according to the comparison results and the comparison completion signals.

Description

BACKGROUND1. Field of the Disclosure[0001]The present disclosure generally relates to analog-to-digital converters (ADCs), and, more particularly, to pipelined ADCs (also called pipeline ADCs).2. Description of Related Art[0002]FIG. 1 is a conventional pipelined analog-to-digital converter(ADC) 100 comprising a plurality of serially connected operation stages 110, a terminal ADC 120, and a digital correction circuit 130. The input signal Vin is subjected to multi-stage operations of comparison, subtraction, and amplification, and finally the correction circuit 130 generates a digital code D by correcting the output of each operation stage 110 and the output of the terminal ADC 120. The digital code D is the result of analog-to-digital conversion of the input signal Vin. The operating principles of the pipelined ADC 100 are well known to those of ordinary skill in the art and shall be omitted herein for brevity.[0003]The operation stage 110 includes a sub-ADC 200 (as shown in FIG. 2)...

AI Technical Summary

Benefits of technology

This approach mitigates voltage disturbances, allowing for a faster response speed and reduced power consumption in pipelined ADCs by ensuring capacitor voltages settle before the amplification phase, thus improving operational stability and efficiency.

Problems solved by technology

The instantaneous voltage change may probably cause disturbances in the voltages on the capacitors C1a and C1b. These voltage disturbances cause unexpected voltage fluctuations at the inputs of the operational amplifier 310 via the switches S4a and S4b, which in turn cause the output voltages of the operational amplifier 310 in an extremely unstable state.

A longer response time, however, means that the pipelined ADC has a slower response speed, or that the pipelined ADC needs a greater driving current to operate at the same response speed.

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