Stacked package including exterior conductive element and a manufacturing method of the same

Abstract

A stacked package has plurality of chip packages stacked on active surfaces of each other, a dielectric layer, a redistribution layer and a plurality of external terminals. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on at least one of the lateral side of the chip package. The dielectric layer, the redistribution layer and the external terminals are formed in sequence on the lateral side with the exposed cut edges to form the electrical connection between the cut edges, the redistribution layer and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.

Description

BACKGROUND OF THE INVENTION1. Field of the Invention[0001]The present invention relates to a semiconductor package, and in particular to a stacked package and a manufacturing method of the same.2. Description of the Prior Arts[0002]Stacking a plurality of chips has been implemented in various semiconductor packages to achieve miniaturization of component integration. The wire bonding method and the through silicon via (TSV) with micro bump are conventional ways to provide electrical interconnection between the stacked chips and the external terminals. However, the conventional ways have following disadvantages.[0003]When the chips are connected to the external terminals by wire bonding, the intervals between the bonding wires need to be preserved to avoid contacts between the adjacent bonding wires. The intervals inevitably increase the size of the conventional stacked package. Thus, the conventional stacked package with bonding wires does not easily achieve miniaturization. In addi...

AI Technical Summary

Benefits of technology

The present invention provides a stacked package and a manufacturing method with higher reliability and better performance. The package has multiple chip packages stacked on each other, a dielectric layer, a redistribution layer, and external terminals. Each chip package has a cut edge on its active surface. The dielectric layer, redistribution layer, and external terminals are then formed in sequence on the chip package's lateral side with the exposed cut edges to form electrical connections. This simplifies the process of forming electrical connections, improving reliability and performance of the package.

Problems solved by technology

The intervals inevitably increase the size of the conventional stacked package.

Thus, the conventional stacked package with bonding wires does not easily achieve miniaturization.

In addition, the wire bonding process takes a lot of time since all of the wires for one conventional stacked package cannot be bonded simultaneously.

Therefore, the unit per hour (UPH) of the conventional stacked package manufactured by the wire bonding process is relatively low.

When the chips are connected to each other by the TSV and the micro bumps, the TSV increases stacked heights and processing complexity leading to larger package thickness and lower manufacturing yield.

When the dimension of the conventional stacked packages become larger and larger, the position shift of the micro bumps becomes greater and greater leading to poor packaging yield.

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