Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Hierarchical power analysis using improved activity abstraction and capacitance abstraction by accounting for design heterogeneity extremities

a technology applied in the field of chip power analysis, can solve the problems of significant heterogeneity in the power profile across the chip, affecting cost and reliability, and consuming a lot of chip power, so as to improve macro activity abstraction, improve and improve the effect of activity abstraction and capacitance abstraction

Active Publication Date: 2021-07-08
IBM CORP
View PDF0 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent describes a method for analyzing power consumption in computer circuits. This method takes into account the design of the circuit and the way it is used. By extracting information about the design, the method generates improved data on how the circuit will behave when it is used. This information is then used to analyze the power consumption of the circuit. The result is more accurate information on the power consumption of the circuit, which can help in designing more efficient circuits.

Problems solved by technology

Modern fin field-effect transistor (FinFET-based) microprocessors' dynamic power consumes a lot of chip power under high utilization conditions.
Power consumption is important in design because it affects cost and reliability.
In addition to heterogeneity across workloads, there is notable heterogeneity in power profile across the chip, even within IP blocks.
One of the difficulties in designing modern microprocessors is swift, accurate power modeling.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Hierarchical power analysis using improved activity abstraction and capacitance abstraction by accounting for design heterogeneity extremities
  • Hierarchical power analysis using improved activity abstraction and capacitance abstraction by accounting for design heterogeneity extremities

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0008]Exemplary methods, apparatus, and products for hierarchical power analysis using improved activity abstraction and capacitance abstraction by accounting for design heterogeneity extremities in accordance with the present disclosure are described with reference to the accompanying drawings, beginning with FIG. 1. FIG. 1 sets forth a block diagram of automated computing machinery comprising an exemplary computing system (152) or host processor configured for hierarchical power analysis using improved activity abstraction and capacitance abstraction by accounting for design heterogeneity extremities according to embodiments of the present disclosure. The computing system (152) of FIG. 1 includes at least one computer processor (156) or “CPU” as well as random access memory (168) (“RAM”) which is connected through a high speed memory bus (166) and bus adapter (158) to processor (156) and to other components of the computing system (152).

[0009]Stored in RAM (168) is a power modelin...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

Method, apparatus and computer program product for hierarchical power analysis using improved activity abstraction and capacitance abstraction by accounting for design heterogeneity extremities comprising extracting design heterogeneity extremities from an RTL design; accounting for the design heterogeneity extremities during macro clock and data signals activity abstraction to generate improved macro activity abstractions; accounting for the design heterogeneity extremities during macro clock and data switching capacitance abstraction to generate improved macro capacitance abstractions; and using improved macro activity abstractions and improved macro capacitance abstractions during hierarchical chip power analysis.

Description

BACKGROUNDField of the Invention[0001]The field of the present disclosure is chip power analysis, or, more specifically, methods, apparatus, and products for hierarchical power analysis using improved activity abstraction and capacitance abstraction by accounting for design heterogeneity extremities.Description of Related Art[0002]Modern fin field-effect transistor (FinFET-based) microprocessors' dynamic power consumes a lot of chip power under high utilization conditions. Power consumption is important in design because it affects cost and reliability. Microprocessors cater to a broad range of workloads, and each workload has a unique power signature. In addition to heterogeneity across workloads, there is notable heterogeneity in power profile across the chip, even within IP blocks. Microprocessor designs are power aware in order to control power consumption.[0003]One of the difficulties in designing modern microprocessors is swift, accurate power modeling. Particularly as devices...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(United States)
IPC IPC(8): G06F30/327G06F30/3323G06F30/3308
CPCG06F30/327G06F2119/06G06F30/3308G06F30/3323G06F30/367G06F30/38G06F2115/10
Inventor JOSEPH, ARUNRACHAMALLA, SPANDANA V.RAO, RAHULREDDY, SHASHIDHAR
Owner IBM CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products