Hierarchical power analysis using improved activity abstraction and capacitance abstraction by accounting for design heterogeneity extremities
a technology applied in the field of chip power analysis, can solve the problems of significant heterogeneity in the power profile across the chip, affecting cost and reliability, and consuming a lot of chip power, so as to improve macro activity abstraction, improve and improve the effect of activity abstraction and capacitance abstraction
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[0008]Exemplary methods, apparatus, and products for hierarchical power analysis using improved activity abstraction and capacitance abstraction by accounting for design heterogeneity extremities in accordance with the present disclosure are described with reference to the accompanying drawings, beginning with FIG. 1. FIG. 1 sets forth a block diagram of automated computing machinery comprising an exemplary computing system (152) or host processor configured for hierarchical power analysis using improved activity abstraction and capacitance abstraction by accounting for design heterogeneity extremities according to embodiments of the present disclosure. The computing system (152) of FIG. 1 includes at least one computer processor (156) or “CPU” as well as random access memory (168) (“RAM”) which is connected through a high speed memory bus (166) and bus adapter (158) to processor (156) and to other components of the computing system (152).
[0009]Stored in RAM (168) is a power modelin...
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