Novel RTOS/OS Architecture for Context Switching Without Disabling Interrupts

Abstract

The present invention is a novel RTOS / OS architecture that changes the fundamental way that context switching is performed. In all prior operating system implementations, context switching required disabling of interrupts. This opens the possibility that data can be lost. This novel approach consists of a context switching method in which interrupts are never disabled. Two implementations are presented. In the first implementation, the cost is a negligible amount of memory. In the second, the cost is only a minimal impact on the context switching time. This RTOS / OS architecture requires specialized hardware. Concretely, an advanced interrupt controller that supports nesting and tail chaining of prioritized interrupts is needed (e.g. the Nested Vectored Interrupt Controller (NVIC) found on many ARM processors). The novel RTOS / OS architecture redefines how task synchronization primitives such as semaphores and mutexes are released. Whereas previous architectures directly accessed internal structures, this architecture does so indirectly by saving information in shared buffers or setting flags, and then activating a low priority software interrupt that subsequently interprets this data and performs all context switching logic. The software interrupt must be set as the single lowest priority interrupt in the system.

Description

REFERENCE TO PROVISIONAL APPLICATION AS PER 35 U.S.C. § 119(e)[0001]Title of Invention: Novel RTOS / OS Architecture For Context Switching Without Disabling Interrupts[0002]application No. 62 / 739,242[0003]Filing Date: Sep. 30, 2018FIELD OF THE INVENTION[0004]This invention is within the field of computer systems software, and in particular, real-time operating systems and operating systems. It addresses the ability of such systems to retrieve incoming data from external hardware peripherals, and the time it takes for such systems to begin processing this data. Specifically, the invention relates to how interrupts and context switching are implemented in such systems.BACKGROUND[0005]The ability of a computer to receive data from external hardware sources (peripherals) is a fundamental functionality. In the beginning, computers would simply only ever execute the very next instruction. Within a loop, the computer would check for new data from all peripherals. When a particular peripheral...

AI Technical Summary

Benefits of technology

This solution ensures constant and efficient data processing response times without data loss, even in high-data-rate scenarios, by maintaining interrupt enablement and minimizing context switching overhead, thus addressing the limitations of traditional context switching methods.

Problems solved by technology

Not all computers include such an interrupt controller.

Thus far, operating system software has failed to properly exploit these advanced interrupt controllers.

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