Semiconductor device and method for fabricating the same

Abstract

Disclosed is a semiconductor device having a double dielectric layer, wherein the double dielectric layer comprises a first dielectric layer having aluminum and a second dielectric layer, of which a dielectric constant is higher than that of the first dielectric layer, stacked on the first dielectric layer. Also disclosed are methods for fabricating the semiconductor device.

Description

FIELD OF THE INVENTIONThe present invention relates to semiconductor devices and methods for making the same; and, more particularly, to semiconductor devices having a dielectric layer of a stacked structure and methods for their fabrication.DESCRIPTION OF THE PRIOR ARTGenerally, a SiO2 layer, which is grown by a rapid thermal treatment process, has been used as gate oxide layers in DRAM or logic device in semiconductor devices. As a design rule, the size of a semiconductor device has been decreased to a tunneling effective thickness (Teff) of 25 Å to 30 Å, which is the tunneling limitation of the SiO2 layer. An appropriate thickness of the SiO2 layer is about 25 Å to 30 Å in a semiconductor device of a 0.1 μm size. However, since off-current increases from direct tunneling, operation of the semiconductor device is deteriorated. Thus, it is beneficial to reduce current leakage in memory devices.To solve this problem, high-k dielectric materials have been researched for use in gate o...

AI Technical Summary

Benefits of technology

The present invention provides a semiconductor device having a dielectric layer having sufficient capacitance required in high integration semiconductor devices and which protects against increases in current leakage and deterioration of dielectric characteristics due to impurities remaining in the dielectric layer.

Problems solved by technology

However, since off-current increases from direct tunneling, operation of the semiconductor device is deteriorated.

When the height of a capacitor increases, the desired focusing depth cannot be obtained by post exposing processes due to a difference in height between a cell of the capacitor and adjacent circuits.

This causes a bad effect on an integration process.

As mentioned the above, a capacitor using a NO layer as a dielectric layer can not be applied to a next generation memory device of over a 256 Mb memory device because it is difficult to obtain desired capacitance.

However, when a simply stacked structure is used in a capacitor, there is a limitation to increase capacitance.

However, there is a limitation on having sufficient capacitance of the SiO2 / Si3N4 (or SiOxNy / Si3N4) layer.

A current leakage of the capacitor increases due to impurities, such as the carbon atoms, ions, radicals and the like, and the dielectric characteristics are deteriorated.

However, this requires undesirable complex processing.

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