Input buffer circuit having function of canceling offset voltage

Inactive Publication Date: 2005-03-29
MITSUBISHI ELECTRIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

It is an object of the present invention to obtain an input buffer circuit without a drop of a capability of a circuit and a limitation of a connection type with a circuit of a former stage.

Problems solved by technology

However, according to the conventional input buffer circuit, a problem arises that there is a case that a capability of the input buffer circuit drops that a noise increases, a bandwidth of the differential amplifier circuit becomes narrow and so on under the influence of the circuit elements described above which are connected with the data path.
Moreover, a case can arise that the offset voltage cannot be appropriately canceled under the influence of a DC component included in a signal outputted from a circuit of a former stage.
Accordingly, a problem arises that a connection type with a circuit of a former stage is limited to a connection type through a capacitor (a capacity coupling type).

Method used

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  • Input buffer circuit having function of canceling offset voltage
  • Input buffer circuit having function of canceling offset voltage
  • Input buffer circuit having function of canceling offset voltage

Examples

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embodiment 1

Preferred

FIG. 1 is a circuit diagram illustrating a composition of an input buffer circuit according to the preferred embodiment 1 of the present invention. The input buffer circuit having a composition that two differential amplifier circuits are in a cascade connection with each other is illustrated in FIG. 1. However, the number of the differential amplifier circuit is not limited to two, but the input buffer circuit only has to include one or more differential amplifier circuits.

The input buffer circuit includes a differential amplifier circuit of a first stage, a differential amplifier circuit of a second stage, a first and a second low pass filter circuits functioning as an integration circuit and a differential amplifier circuit 5 functioning as a voltage converting circuit. In this regard, a level shifter circuit can be placed in exchange for the differential amplifier circuit 5.

The differential amplifier circuit of the first stage has loads 1m and 1n and n channel MOLESTS (...

embodiment 2

Preferred

FIG. 3 is a circuit diagram illustrating a composition of an input buffer circuit according to the preferred embodiment 2 of the present invention. The first output terminal of the differential amplifier circuit 5 is connected with the respective back gates of the transistors 1x and 2x, respectively. According to this, the voltage V3a is impressed on the respective back gates of the transistors 1x and 2x by the differential amplifier circuit 5, respectively. Moreover, the second output terminal of the differential amplifier circuit 5 is connected with the respective back gates of the transistors 1y and 2y. According to this, the voltage V3b is impressed on the respective back gates of the transistors 1y and 2y by the differential amplifier circuit 5, respectively. Other composition of the input buffer circuit according to the present preferred embodiment 2 is similar to the composition of the input buffer circuit according to the preferred embodiment 1 described above as sh...

embodiment 3

Preferred

FIG. 4 is a circuit diagram illustrating a composition of an input buffer circuit according to the preferred embodiment 3 of the present invention. A first input terminal of the differential amplifier circuit 51 (also called “voltage converting circuit” in the present preferred embodiment 3) is connected with a serial connection point between the resistance 3s and the capacitor 4s. According to this, a voltage value V2a outputted from the first low pass filter circuit is inputted to the first input terminal of the differential amplifier circuit 51. Moreover, a second input terminal of the differential amplifier circuit 51 is connected with a serial connection point between the resistance 3t and the capacitor 4t. According to this, a voltage value V2b outputted from the second low pass filter circuit is inputted to the second input terminal of the differential amplifier circuit 51.

The differential amplifier circuit 51 outputs a voltage V3a1 with converting the voltage value ...

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Abstract

An input buffer circuit without a drop of a capability of a circuit and a limitation of a connection type with a circuit of a former stage is obtained. The output signal (OUTB) is inputted to a first low pass filter circuit, and the first low pass filter circuit integrates the output signal (OUTB). A result of the integration is stored as a voltage value (V2a) in the capacitor (4s). In the same manner, an output signal (OUT) is inputted to a second low pass filter circuit, and the second low pass filter circuit integrates the output signal (OUT). A result of the integration is stored as a voltage value (V2b) in a capacitor (4t). A differential amplifier circuit (5) generates appropriate voltages (V3a and V3b) according to a design specification of the transistors (1x and 1y) by amplifying the voltage values (V2a and V2b) and outputs them. The voltages (V3a and V3b) are impressed on respective back gates of the transistors (1x and 1y), respectively.

Description

BACKGROUND OF THE INVENTION1. Field of the InventionThe present invention relates to an input buffer circuit having a function of canceling an offset voltage.2. Description of the Background ArtIn a conventional input buffer circuit having a composition that plural differential amplifier circuits are in a cascade connection with each other, various circuit elements such as a resistance for a voltage division, a terminating resistance and so on are connected with a data path (or a signal path) to cancel an offset voltage.Besides, a technique corresponding to a method of canceling the offset voltage is disclosed in Japanese Patent Application Laid-Open Nos. 2002-9561, 2003-8407 and H04-192703 (1992).However, according to the conventional input buffer circuit, a problem arises that there is a case that a capability of the input buffer circuit drops that a noise increases, a bandwidth of the differential amplifier circuit becomes narrow and so on under the influence of the circuit eleme...

Claims

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Application Information

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IPC IPC(8): H03F3/45H03K19/0175H04L25/02
CPCH03F3/45748H03F2203/45652H03F2203/45342
InventorTAKATA, KENGOYOSHIMURA, TSUTOMUKONDO, HARUFUSAITO, HIRONOBU
OwnerMITSUBISHI ELECTRIC CORP