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Computer system initialization via boot code stored in a non-volatile memory having an interface compatible with synchronous dynamic random access memory

a non-volatile memory and computer system technology, applied in the field of computer system, to achieve the effect of reducing the number of interface lines and non-volatile memory devices

Active Publication Date: 2006-06-06
MEDIATEK INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0008]The present invention seeks to reduce the number of interface lines and non-volatile memory devices in a computer system. The present invention provides for a computer system wherein the non-volatile memory shares a common interface with SDRAM. In particular, the present invention provides for a non-volatile memory that has an SDRAM style memory interface, being used to provide initialization (boot) code to the computer system; eliminating any need for an additional random access non-volatile memory to provide boot code.

Problems solved by technology

The initializing information is stored in the non-volatile memory, e.g., Flash memory, which creates a dilemma since the non-volatile memory uses an SDRAM interface for which the logic has yet to be initialized.

Method used

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  • Computer system initialization via boot code stored in a non-volatile memory having an interface compatible with synchronous dynamic random access memory
  • Computer system initialization via boot code stored in a non-volatile memory having an interface compatible with synchronous dynamic random access memory
  • Computer system initialization via boot code stored in a non-volatile memory having an interface compatible with synchronous dynamic random access memory

Examples

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Embodiment Construction

[0017]A typical computer system 10 is shown in FIG. 1. The system 10 is implemented on a motherboard 12, and includes a processor or central processing unit (CPU) 14 also known as a micro-controller or micro-processor, a volatile random access memory 16, a volatile sequential access memory in the form of SDRAM 18, and non-volatile memory 20. A power supply 22 is provided on the motherboard 12 in a conventional manner, and an input / output (I / O) unit 24 provides an interconnection of the motherboard 12 to typical I / O devices such as a display monitor 26, keyboard 28, and one or more disk drives 30. These components are interconnected by signal buses, power lines, connectors, etc., as collectively indicated at 32. The non-volatile memory 20 has the same interface as the SDRAM.

[0018]The boot code for initializing the SDRAM interface logic, the internal logic of the SDRAM, and the rest of the system is stored in the non-volatile memory 20, which may be Flash memory.

[0019]Referring to FIG...

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PUM

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Abstract

A method for reducing the number of interface lines and non-volatile memory devices in a computer system includes providing a non-volatile memory having a SDRAM style interface. A system having both non-volatile memory and SDRAM has reduced interface lines by providing only one memory interface. A system where the SDRAM interface logic is initialized by code stored in the non-volatile memory having a SDRAM style interface, eliminating any requirement for other non-volatile memory, independent of the SDRAM interface, from which to initialize the system.

Description

[0001]This application claims the benefit of U.S. Provisional Application No. 60 / 273,616, filed Mar. 5, 2001.FIELD OF THE INVENTION[0002]The invention relates to a computer system and a method of implementing a computer system having a non-volatile memory and a volatile memory. In particular, it relates to a computer system in which the non-volatile memory and volatile memory have a sequential access mode of operation.BACKGROUND OF THE INVENTION[0003]Computer systems typically include both non-volatile memory, for storing information that has to be retained at power-off, as well as volatile memory.[0004]Dynamic random access memory (DRAM) is a commonly used volatile system memory. It uses an interface with address lines that are typically multiplexed in time. Thus, an address having twice the number of bits as there are address lines is supplied in two successive stages. The most and least significant portions of a complete address are presented sequentially. This arrangement reduce...

Claims

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Application Information

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IPC IPC(8): G06F12/00
CPCG06F9/4403
Inventor MCCLAIN, MARK ALAN
Owner MEDIATEK INC