Clock recovery circuit

Abstract

A clock recovery circuit comprises a phase comparator detecting phase differences between input data and sampling clocks and outputs them as pulse signals of two values of advanced and delayed, a low-pass filter reducing frequencies of the pulse signals outputted from the phase comparator and outputs reduced frequencies, a control signal generator monitoring the reduced frequencies and generates a phase control signal used to adjust the phase of each sampling clock to be small or large based on the ratio of the advanced and delayed signals, a phase interpolator adjusting the phase of each sampling clock upon receiving the phase control signal, and a frequency divider dividing the sampling clock having the adjusted phase by a predetermined frequency division ratio to output it, and controls the low-pass filter and control signal generator based on the frequency divided output.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2002-089773, filed Mar. 27, 2002, the entire contents of which are incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a clock recovery circuit which is used for, e.g., high-speed data communication.[0004]2. Description of the Related Art[0005]In a data communication system, in order to perform serial transmission between communication devices having clock signal sources different from each other, a communication device on a reception side requires clocks with the same frequency as that of a communication device on a transmission side. In this case, the reception side generates a sampling clock synchronized with reception data so as not to generate a frequency offset, and samples the reception data by using this clock, thereby acquiring reproduction ...

AI Technical Summary

Benefits of technology

[0011]a low-pass filter which reduces the pair of first frequencies in accordance with a frequency reducing control signal which specifies a frequency reduction ratio, and outputs a pair of second frequencies;

[0012]a control signal generator which monitors the pair of second frequencies, and generates a phase control signal used to adjust phases of the sampling clocks to be small when the advanced signal and the delayed signal are outputted substantially evenly as the pair of second frequencies, and to adjust the phases of the sampling clocks to be large when one of the advanced signal and the delayed signal is larger in number than the othe

Problems solved by technology

However, the prior art clock recovery circuit cannot correct a phase of the sampling clock to an ideal position immediately even though it tries to correct the phase of the sampling clock to the ideal position when a period with no transition of a value of the reception data is long, which leads to a problem of many reading errors of the reception data.

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