Content addressable memory (CAM) cell bit line architecture

Abstract

A ternary content addressable memory (TCAM) cell (100) can include two memory elements (102-0 and 102-1) with a single bit line (106-0 and 106-1) per memory element. A TCAM cell (100) can also include a compare stack (104) and two word lines (114 and 116) that can connect to each memory element (102-0 and 102-1). The memory elements (102-0 and 102-1) can include SRAM type memory cells with one of two data terminals connected to a pre-write potential (Vpre, which can be a ground potential, or the like). Write operations can include pre-setting the data values of memory elements (102-0 and 102-1) to the pre-write potential prior to providing write data via the bit lines (106-0 and 106-1).

Description

[0001]This application claims the benefit of U.S. Provisional Patent Application Ser. No. 60 / 506,679 filed on Sep. 26, 2003, and is a divisional of U.S. Nonprovisional patent application Ser. No. 10 / 931,960 filed Aug. 31, 2004, now U.S. Pat. No. 7,173,837.TECHNICAL FIELD[0002]The present invention relates generally to integrated circuits, and more particularly to content addressable memory (CAM) circuits having ternary CAM cells.BACKGROUND OF THE INVENTION[0003]Content addressable memory (CAM) device enjoy wide use in a variety of applications, including high speed switches and routers for communications. CAM devices can include both binary CAMs and ternary CAMs. Binary CAM devices can include bit locations for accommodating two stored states for comparison: “0” or “1”. Ternary CAM (TCAM) devices can include bit locations for accommodating three states for comparison: “0”, “1”, or “X” (where X is a don't care term, that provides a match regardless of the compare data value).[0004]On...

AI Technical Summary

Benefits of technology

[0015]In such an arrangement, second controllable impedance paths can allow the memory elements to be pre-set to certain logic values prior to a write. Such an arrangement can allow for more stable writing of data values into the CAM cell.

[0022]Such an arrangement can provide for a CAM cell having one bit line per storage element that can be utilized with a “pseudo-ground” arrangement, which can have low charge consumption advantages.

[0030]In this way, an SRAM cell can be pre-set to a particular data value prior to the writing of data into the cell. This can provide for more stable write operations.

[0036]In this way, reductions in the number of bit lines, can allow for greater pitch in those lines routed in the same direction as the bit lines, such as compare data lines.

[0038]Such an arrangement can allow for faster compare operations, as wider compare data lines can provide a lower resistance.

Problems solved by technology

As a result, a pitch for compare data lines (CD and CDB is limited in order to accommodate bit line pairs in the same direction.

A drawback of the above alternate conventional approach can be increased design risk and complexity resulting from the application of different word line voltages for read and write operations.

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