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Constant voltage power supply circuit

a constant voltage power supply and circuit technology, applied in the direction of electric variable regulation, process and machine control, instruments, etc., can solve the problems of driving delay that may vary the output voltage, tend to larger gate capacitance,

Inactive Publication Date: 2010-12-28
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The proposed circuit effectively reduces output voltage variations while maintaining stability across varying load currents, achieving a drop width of 60 mV or less with a delay time of 12 nS or less, improving performance over conventional designs.

Problems solved by technology

This causes a tendency towards larger gate capacitance.
A rapid change of the output current may, however, cause a driving delay that may vary the output voltage.

Method used

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first embodiment

[0022]With reference to the drawings, a constant voltage power supply circuit according to a first embodiment of the present invention will be described below. FIG. 1 is a circuit diagram showing circuitry of a series regulator 10 as a constant voltage power supply circuit. FIG. 2 shows an example of how the series regulator 10 may be utilized.

[0023]The series regulator 10 receives an input voltage VIN (for example, a power supply voltage VDD) at an input terminal 1. The regulator 10 has a function of decreasing and stabilizing the input voltage to provide a constant output voltage VOUT at an output terminal 2. The series regulator 10 includes a chip enable terminal 3 and a ground terminal 4. The chip enable terminal 3 receives a chip enable signal that instructs the start of the circuit operation. The ground terminal 4 is given a ground potential VSS.

[0024]With reference to FIG. 2, the series regulator 10 may be used, for example, to receive the power supply voltage VDD from a powe...

second embodiment

[0044]With reference to FIG. 5, a second embodiment of the present invention will now be described. FIG. 5 shows only the configuration of the main portion near the discharge circuit 17 in the series regulator 10 according to the second embodiment of the present invention. The other portions are similar to those in the first embodiment (FIG. 1), and so their detailed description is omitted here.

[0045]In this embodiment, the input signal Wakeup′ from the CPU 31 is not a pulse signal having a short pulse width of about 30 nS. Alternatively, the Wakeup′ is a signal that rises from “L” to “H” when the decrease of the output current IOUT is sensed and then holds “H.”

[0046]It may be overload for the CPU 31 in the semiconductor integrated circuit 30 (the output load) to control the pulse width of the input signal Wakeup′. A pulse generation circuit 50 as shown in FIG. 5 may then be provided to reduce the load of the CPU 31 and more accurately control the pulse width.

[0047]With reference to...

third embodiment

[0049]With reference to FIG. 6, a third embodiment of the present invention will now be described. FIG. 6 shows only the configuration of the main portion near the discharge circuit 17 in the series regulator 10 according to the third embodiment of the present invention. The other portions are similar to those in the first embodiment (FIG. 1), and so their detailed description is omitted here.

[0050]In this embodiment, like the second embodiment, the input signal Wakeup′ is not a pulse signal having a short pulse width of about 30 nS. Alternatively, the Wakeup′ is a signal that rises from “L” to “H” when the decrease of the output current IOUT is sensed and then holds “H.” A counter circuit 60 is provided to convert the input signal Wakeup′ to the input signal Wakeup having a pulse width of about 30 nS. The counter circuit 60 receives the input signal Wakeup′ and a clock signal CLK having a cycle of, for example, about 5 nS. After the input signal Wakeup′ rises from “L” to “H,” the c...

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Abstract

A first output transistor forms a first current path between an input and an output terminal and has a first control terminal applied with a first control signal. A second output transistor forms a second current path between the output and a ground terminal and has a second control terminal applied with a second control signal. A first comparator outputs the first control signal to decrease an ON-resistance of the first transistor when an output voltage from the output terminal is a predetermined value or less. A second comparator outputs the second control signal to render the second transistor conductive to decrease the output voltage when the output voltage is a predetermined value or more. An acceleration circuit accelerates charging of the first control terminal of the first transistor to a predetermined potential. The inhibition circuit inhibits the acceleration circuit operation according to a change of the second control signal.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application is based on and claims the benefit of priority from prior Japanese Patent Application No. 2007-274002, filed on Oct. 22, 2007, the entire contents of which are incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a constant voltage power supply circuit adapted to output a constant voltage.[0004]2. Description of the Related Art[0005]One known constant voltage power supply circuit includes a series linear regulator including a CMOS circuit (see, for example, JPH 2007-219856). The series linear regulator contains a reference voltage generation circuit that generates a reference voltage, a comparator that compares the reference voltage and the output voltage, and a pMOS transistor driven by the comparator.[0006]The pMOS transistor is connected between the input terminal and the output terminal. The input terminal receives an input voltage Vin (i.e.,...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G05F1/575G05F1/595
CPCG05F1/56
Inventor YAMASHITA, TAKAHIRO
Owner KK TOSHIBA