Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario models

Abstract

A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

Description

CLAIM OF PRIORITY[0001]This application claims the benefit of and priority to, under 35 U.S.C. 119§(e), to U.S. Provisional Patent Application No. 61 / 981,711, filed on Apr. 18, 2014, and titled “Graphics Based SOC Design Tool”, which is hereby incorporated by reference in its entirety.FIELD[0002]The present embodiments relate to testing a system-on-a-chip with portable scenario models and at different horizontal and vertical levels.BACKGROUND[0003]A system-on-a-chip (SoC) integrates all components of a computer or another electronic system on a chip. The SoC includes software and hardware. The SoC is used with other SoCs to develop a system for performing a number of functions, e.g., printing, receiving data, sending data, receiving phone calls, playing virtual games, etc.[0004]Hardware blocks of SoCs are designed using a software tool, e.g., a computer-aided design (CAD) tool. Also, software drivers that control the hardware blocks are integrated within the design. The SoCs are ver...

AI Technical Summary

Benefits of technology

The patent text describes a method for generating test cases for electronic circuits. By using a portable scenario model, the same test cases can be used at different stages of the project, without having to develop new ones. This saves time and money and ensures that bugs are caught early on, reducing the risk of delays and missed market windows. Overall, this method improves the efficiency of the testing process and increases the likelihood of successful projects.

Problems solved by technology

Second, the random input stimulus may not exercise all functions of interest to test the DUT.

Moreover, as designs increase in complexity, a large amount of design functions are not exercised using the random input stimulus.

This is expensive and time consuming.

Furthermore, some verification test cases are tied to specific test benches and cannot be applied across all stages of a project.

Redeveloping these tests for the different stages is expensive and time consuming.

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