Method of forming a semiconductor device and according semiconductor device

Abstract

The present disclosure provides a method of forming a semiconductor device, including a shaping of a gate structure of the semiconductor device such that a spacer removal after silicide formation is avoided and silicide overhang is suppressed. In some aspects of the present disclosure, a method of forming a semiconductor device is provided wherein a gate structure is provided over an active region of a semiconductor substrate, the gate structure including a gate electrode material and sidewall spacers. At least one of the gate electrode material and the sidewall spacers are shaped by applying a shaping process to the gate structure and a silicide portion is formed on the shaped gate structure.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present disclosure relates to a method of forming a semiconductor device and to a semiconductor device. Particularly, the present disclosure relates to processing at the end of front-end-of-line (FEOL) fabrication.[0003]2. Description of the Related Art[0004]In modern electronic equipment, integrated circuits (ICs) experience a vast applicability in a continuously spreading range of applications. Particularly, the demand for increasing mobility of electronic devices at high performance and low energy consumption drives developments to more and more compact devices having features with sizes ranging even into the deep submicron regime; the more so as current semiconductor technologies are apt of producing structures with dimensions in the magnitude of 10 nm. With ICs representing a set of electronic circuit elements integrated on a semiconductor material, normally silicon, ICs can be made much smaller than discreet c...

AI Technical Summary

Benefits of technology

The present patent is about a method for making a semiconductor device. It describes a way to shape the gate structure of the device in a way that avoids the removal of a spacer after the formation of silicide and also helps to prevent silicide from overhanging. This technique can improve the manufacturing process of semiconductor devices.

Problems solved by technology

The silicon recess and the corresponding silicide loss caused by process 170 poses the risk of causing ILD pinching during subsequent ILD-related process steps, such as TPEN deposition.

In consequence, upon increasing the integration density of semiconductor devices on the semiconductor substrate 100, space between two neighboring gate structures 120 and 140 is reduced, leading to various problems, such as an unacceptably reduced process margin for contact to gate shorts and an increased parasitic capacitance between contacts and gate electrodes.

Further issues arise with regard to the deposition of subsequent ILD layers, such as difficulties in depositing ILD layers without potential voids in the ILD layer due to the reduced distance b and resulting tungsten vias deteriorating device performance.

Furthermore, due to the aggressive etch chemistry of the process 170 in FIG. 1a, a high silicon / silicide loss is created, causing further sub-optimal profiles for subsequent ILD layers, such that the problem of potential voids is increased rather than decreased.

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