Method for forming a via plug in a semiconductor device
a technology of semiconductor devices and vias, which is applied in the direction of semiconductor devices, semiconductor/solid-state device details, electrical apparatus, etc., can solve the problems of increasing the adhesive strength to the contact surface of the via hall, lowering the electrical connection characteristic of the semiconductor device, and reducing the via resistance. , to achieve the effect of increasing the surface area of the adhesive contact area, increasing the adhesive strength, and decreasing the via resistan
Inactive Publication Date: 2004-01-13
HYUNDAI ELECTRONICS IND CO LTD
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Benefits of technology
"The present invention provides a method for making a via plug in a semiconductor device. The method involves depositing layers of metal and insulation on a substrate, planarizing the insulation layer, etching the layers to form a via hole, and pretreating the via hole before depositing metal on the first metal layer. This process results in the formation of metal nuclei and etching grooves on the first metal layer, which can improve the reliability and performance of the semiconductor device."
Problems solved by technology
The formation of such grooves has the effect of increasing the bottom surface area of the via hall, thereby increasing the adhesive strength to a contact surface of the via hall and decreasing the via resistance.
Accordingly, when the via plug is formed on the via halls, the tungsten is deposited with a lack of uniformity resulting in increased via resistance to; such increased resistance has a deleterious effect on subsequent processes culminating in the lowering of the electrical connecting characteristic of the semiconductor device.
Method used
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Embodiment Construction
FIGS. 1A through 1E are cross sectional views illustrating steps forming a via hole in a semiconductor device according to the present invention.
Referring to FIG. 1A, a first metal layers 2 are initially formed on the substrate 1 in such a way so as to be isolated from each other. The first, second and third insulating layers 3, 4 and 5 are sequentially formed on the resulting substrate and then the third insulating layer 5 is planarized.
Referring to FIG. 1B, a desired portion of the first, second and third insulating layers 3, 4 and 5 situated on top of the first metal layers 2 are sequentially etched using the wet etching or dry etching method in order to connect to a second metal layer which will be formed in a later process, and thereby forming via holes 6 the aspect ratios of which are different from each other.
Referring to FIG. 1C, the via holes 6 are pretreated by the dry etching method in the RIE (Reactive Ion Etch) reactor during approximately one (1) minute using a NF.sub....
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Abstract
A method of forming a via plug in a semiconductor device is disclosed. Metal nuclei are formed on the surface of the metal layer underlying the via hole. The metal layer, which is partially exposed between metal nuclei, is etched by means of a wet etching method, and accordingly, a plurality of etching grooves is formed on the partially exposed surface of the metal layer. As a result, the formation of such grooves has the effect of increasing the bottom surface area of the via hall, thereby increasing the adhesive strength to a contact surface of the via hall and decreasing the via resistance.
Description
FIELD OF THE INVENTIONThe invention relates to a method of forming a via plug in a semiconductor device, more particularly, it relates to a method of forming a via plug by forming metal nuclei on the surface of a metal layer underlying a via hall and then etching the metal layer exposed between the metal nuclei by the wet etching method so that a plurality of etching grooves are formed thereupon. The formation of such grooves has the effect of increasing the bottom surface area of the via hall, thereby increasing the adhesive strength to a contact surface of the via hall and decreasing the via resistance.INFORMATION DISCLOSURE STATEMENTGenerally, as integration of a semiconductor device is increased, the size of the via hall diminishes while the aspect ratio increases. If the depth of the via halls are different from each other, the via plug is formed on the via halls using tungsten. In order to form a uniform and complete via plug, pretreatment of the via halls is important. If the...
Claims
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IPC IPC(8): H01L21/70H01L21/768
CPCH01L21/76814H01L21/76877H01L2224/06102
Inventor CHOI, KYEON K.
Owner HYUNDAI ELECTRONICS IND CO LTD