Local space shared memory method of heterogeneous multi-kernel microprocessor

Abstract

This invention discloses a method for sharing and storing local spaces of heterogeneous multi-kernel microprocessors including: applying said system to define part storage spaces of parallel processor kernels as the in-chip shared storage spaces, other storage spaces are not changed and the address of the in-chip stored space is the same to all the parallel processor kernels, which can be accessed except the control processor kernel. The in-chip shared storage spaces are organized to a shared storage pool with multiple storages and an arbitration device is designed to arbitrate the access to the shared storage pool.

Description

Technical field: [0001] The invention relates to a shared memory method for multi-core microprocessors in large-scale integrated circuit design. Background technique: [0002] With the increase of problem scale and the improvement of real-time requirements, the processing ability of single-core microprocessor has been difficult to meet the demand. Advances in microelectronics technology have made it possible to integrate multiple microprocessors on one chip. A multi-core microprocessor contains multiple processors, and tasks can be assigned to each processor under the scheduling of the operating system, providing more powerful processing capabilities and higher parallelism. [0003] According to the types of built-in processor cores, multi-core microprocessors can be divided into two types: homogeneous multi-core microprocessors and heterogeneous multi-core microprocessors. The processor core type contained in the homogeneous multi-core microprocessor is the same, and it i...

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Problems solved by technology

[0007] But these three methods have the following disadvantages: 1) Since the shared data may have multiple backups in the Cache, the hardware overhead for maintaining Cache consistency must be increased

2) Maintaining Cache consistency increases communication overhead and increases the transmission delay of shared data, especially when the calculation / communication ratio decreases, the performance drops significantly

3) Since each processor core contained in the multi-core microprocessor has the same priority for memory access, the possibility of memory access conflicts is high, resulting in increased memory access delays

4) Because of the uniform addressing of the storage space, address conflicts may occur in programs compiled using the original compiler of the processor core. Therefore, the multi-core microprocessor using these shared storage methods must redesign the parallel compiler, which prolongs the development cycle.

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