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Semiconductor device equiped with memory and logical chips for testing memory ships

A memory chip and memory testing technology, which is applied to semiconductor devices, semiconductor/solid-state device components, static memory, etc., can solve the problems of impossible testing and achieve the effect of high-speed access operation testing

Inactive Publication Date: 2008-03-12
SOCIONEXT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] Even though limited testing is possible on the memory chip 3 in wafer condition, after it is assembled into the package 1 and after the reliability-enhancing burn-in has been completed, various tests are impossible because the memory chip is itself fixed

Method used

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  • Semiconductor device equiped with memory and logical chips for testing memory ships
  • Semiconductor device equiped with memory and logical chips for testing memory ships
  • Semiconductor device equiped with memory and logical chips for testing memory ships

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Embodiment Construction

[0037] specific implementation plan

[0038] Embodiments of the present invention are described with reference to the accompanying drawings. However, the scope of protection of the present invention is not limited to the following embodiments, but it can be extended to the present invention described in the claims and the equivalents thereto.

[0039] Fig. 2 is a general configuration diagram of a semiconductor device in the case of this embodiment. The same reference numerals are used at the same places as in FIG. 1 . In this semiconductor device shown in FIG. 10 , the power terminal 36 and the ground terminal 37 of the memory chip 3 are connected to the external terminal 10 of the package 1 . The memory chip 3 is accessed from the logic chip 2, whose clock terminal 22, control signal terminal 23, address terminal 24 and data terminal 25 are respectively connected to corresponding terminals 32, 33, 34 and 35 of the memory chip.

[0040] The logic chip 2 has a logic circui...

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PUM

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Abstract

The present invention is a semiconductor device wherein a logic chip having prescribed functions and a memory chip for storing data are mounted in a common package, wherein the logic chip and memory chip are connected through such memory access terminals as a control signal terminal, address terminal, and data terminal and the like. The logic chip has a logic circuit having prescribed functions and a memory chip testing circuit for performing operation tests on the memory chip. The logic chip also has a selector-output circuit for selecting a memory access signal from the logic circuit and a memory testing access signal from the memory chip testing circuit to output the selected signal to the memory access terminals.

Description

technical field [0001] The present invention relates to a multi-chip package (MCP) or multi-chip module (MCM) semiconductor device in which a memory chip and a logic chip are mounted, and to a semiconductor device whereby the memory chip can be tested after conditioning in the package is completed. Background technique [0002] Semiconductor devices called MCPs and MCMs, in which a large-capacity memory chip and a logic chip including special functions such as image processing, are housed in the same package are being widely used. FIG. 1 is a configuration diagram of a conventional MCP or MCM semiconductor device. In the common package 1 are mounted a high-speed, large-capacity memory chip 3 such as SDRAM and a logic chip 2 with special functions. Inside the logic chip 2 there is a logic circuit 2A and an input / output circuit 2B of the memory chip 3 , around which are also input / output terminals 20 to 25 . A cell array (not shown) is disposed within the memory chip 3, and ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/00H01L25/00H01L23/52G01R31/28G11C11/401G11C29/02G11C29/12G11C29/48
CPCG11C29/48G11C2029/0401G11C29/1201G11C29/00
Inventor 石川胜哉
Owner SOCIONEXT INC