Data processing system having a Cartesian controller, and method for processing data
A technology for data processing systems and controllers, which is applied to general-purpose stored program computers, etc., and can solve problems such as large downtime
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[0017] Figure 1 shows the connection between a Cartesian controller (CC) 100 and a data processing engine 102 (hereinafter referred to as the connection engine) and the active cell matrix supported therein, or processing element 104 (hereinafter referred to as the connection memory (CM)). structural relationship. The synchronous clock circuit 106 is used to coordinate the operation of CC100, CE102 and CM104, so that CC100 issues one of multiple instructions and transmits them to CE102 and CM104 for parallel execution and processing.
[0018] The clock circuit 106 can output a predetermined number of clock cycles per second, and the CC 100 can perform internal operations such that in a single clock cycle, the CC 100 performs one of multiple internal operations and simultaneously issues one of multiple instructions to the CE 102 . Cache memory 108 and RAM controller 110 are also shown.
[0019] Cache memories 108 constitute buffer pools, each preferably equal in size to CM 104 ...
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