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Charge-trapping semiconductor memory device

A technology for storage devices and charge capture, applied in semiconductor devices, electric solid-state devices, circuits, etc., can solve problems such as limitation, small effective channel length, and difficulty in separating two bits

Inactive Publication Date: 2008-08-13
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But because of the reduction in cell size, the separation of the two bits becomes more and more difficult as the locations for charge storage get closer together, thus forming a size limit for the planar nitride read-only memory cell.
[0007] Further miniaturization of semiconductor memory devices, including charge trapping cells, is limited by the required minimum effective channel length

Method used

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  • Charge-trapping semiconductor memory device
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Embodiment Construction

[0017] The charge trapping semiconductor memory device includes a semiconductor layer or substrate having a major surface, preferably recessed by etching. These recesses serve as locations for respective memory cells, and each includes a transistor structure and a memory layer sequence. figure 1 A cross section is shown through a substrate 1 of semiconductor material, preferably silicon material, into which a cylindrical recess 2 has been etched. figure 1 The ideal icon for shows two cylindrically shaped recesses with a flat bottom area. Practical embodiments of the device may be implemented with a rounded or tapered bottom, depending on the standard etching method. In either case, there is no restriction on the geometry of the recess. Preferably, said recess is cylindrical, but the actual shape may differ from the ideal cylindrical shape. The sidewall of the recess is covered by the storage layer sequence 3 , which is at least disposed in a sidewall region adjacent to the ...

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Abstract

The invention relates to a memory cell in which the concave on the main surface of a semiconductor substrate is best designed to be cylindrical, and comprises store layer series which are arranged on the lateral wall and at a grid electrode part, and an upper and a lower source cathode or drain regions which are connected with a first bit line and a second bit line in the form of row. The first and the second bit lines are provided with word lines which are connected with a grid electrode row. The vertical transistor structure promotes further shrinkage of the unit, and the needed minimum effective channel length is generated.

Description

technical field [0001] The present invention relates to a charge trapping semiconductor memory device, particularly a memory device including a nitride read only memory (NROM) cell. Background technique [0002] Nonvolatile memory cells that are electrically written or erased can be implemented using charge trapping memory cells that include a sequence of memory layers having a dielectric material and memory layers interposed between confining layers of the dielectric material , the dielectric material confinement layer has a larger energy band gap than the storage layer. [0003] The storage layer sequence is disposed between channel regions in a semiconductor layer or substrate, and a gate is provided to control the channel by applying voltage. Writing to the cell is accomplished using the acceleration of charge carriers, especially electrons in the channel, to generate charge carriers with sufficient kinetic energy to penetrate the confinement layer and become trapped in...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/112H01L29/78
CPCH01L29/7926H01L29/7881H01L27/11553H01L27/115H01L29/792H01L27/11568H10B69/00H10B41/23H10B43/30
Inventor M·维霍文
Owner INFINEON TECH AG