Memory cells and identification method and memory array and detection method thereof

Abstract

A NROM memory device includes an array of memory cells and first and second bit lines. The first and second bit lines are coupled to opposite sides of the memory cells. During an erase operation, one of the sides of the memory cells receives a positive voltage and the other side couples to a common node or a limited current source. Methods are also disclosed that can easily screen for marginal memory cells based on a threshold voltage distribution of the memory cells.

Description

technical field [0001] The present invention relates to a non-volatile memory, in particular to a device and method for improving the erasure consistency of a nitride read-only memory (NROM) and identifying a marginal memory cell. Background technique [0002] With the increasing demand for consumer electronic products, such as digital cameras, MP3 players, laptop computers and personal digital assistants (PDAs), etc., there is a need to use non-volatile memory devices to store large amounts of data. [0003] A nitride read only memory cell includes an oxide-nitride-oxide (ONO) gate dielectric and a controlling gate on the ONO gate dielectric. It allows two spatially separated charge distributions within the nitride layer of the ONO gate dielectric on the source and drain junctions of the memory cell, respectively. As a result, the ONO dielectric layer can store two bits of information in each memory cell on these nodes. Thus, NROM 2-bit memory cells remain attractive at l...

AI Technical Summary

Problems solved by technology

Variations in uncertain voltage levels can lead to inconsistencies in erasing all memory cells

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