Method for manufacturing of semiconductor device metal connecting hole and semiconductor device

Abstract

The invention discloses a manufacturing method of a metal connecting hole of a semiconductor device. The method comprises the following steps: an MOS device is formed on the surface of a semiconductor substrate. The MOS device comprises a gate, a source area and a leak area, and gate metal silicide is formed on the surface layer of the gate; leak source metal silicide is respectively formed on the surfaces of the source area and the leak area; sidewall partitions comprising a silicon oxide layer and a silicon nitride layer are arranged at the both sides of the gate; the silicon oxide layer on the surface of the substrate is eroded, and therefore dent is formed between the sidewall partitions and the surfaces of the source area and the leak area; a dielectric layer is deposited and is etched to form a through hole, and the source leak metal silicide is exposed from the bottom part of the through hole; an adhesion layer is deposited on the surface of the source leak metal silicide; metal is filled into the through hole to form the metal connecting hole. The method of the invention can prevent the metal silicide from being converted into a high-impedance state and from diffusing towards the trench direction.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a metal connection hole of a metal oxide semiconductor device (MOS) and a semiconductor device including the metal connection hole. Background technique [0002] Today's semiconductor manufacturing technology is developing rapidly, semiconductor devices have a deep submicron structure, and integrated circuits already contain a huge number of semiconductor devices. In such a large-scale integrated circuit, the high-reliability and high-density connection between devices must not only be performed in a single layer, but also between multiple layers. Therefore, multi-layer interconnection structures are usually used for semiconductor devices connect. Before forming the multilayer interconnection structure, it is necessary to deposit a dielectric layer on the surface of the MOS device and form a metal connection hole in the dielectric layer, ...

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Problems solved by technology

During the annealing process, the annealing temperature is usually between 800-1000°C, at this temperature, the metal silicide NiSi will undergo a phase transition from NiSi to NiSi 2 , but NiSi 2 It is in a high-resistance state, and it is an unstable intermediate phase, which will diffuse along the lateral direction to the channel, and form high-resistance metal silicides 151 and 152 in the source region 110 and the drain region 120, so that the connection hole 200 is connected to the source region. The contact resistance between the region 110 and the drain region 120 increases, which affects the performance of the MOS device

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