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Data pre-fetching system in video processing

A technology of data prefetching and video processing, which is applied in the system field of telecommunications technology, and can solve problems such as memory bandwidth consumption, prefetch failure, and data access delay reduction

Inactive Publication Date: 2009-08-05
SHANGHAI JIAOTONG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] According to the literature search of the prior art, it is found that the Chinese patent application number is 200510093077.9, and the patent name is "a cache prefetching module and its method". Into the cache memory, which can reduce cache misses and improve the cache hit rate, but the processor needs to execute more instructions to achieve this function
Some processors use hardware units to predict data access and transfer the required data into the memory, thereby reducing the delay of data access, but this kind of data prefetching that does not require instructions is speculative data prefetching, and there must be prefetch failure. , which consumes the already very limited memory bandwidth

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Embodiment Construction

[0015] The embodiments of the present invention are described in detail below: the present embodiment is implemented under the premise of the technical solution of the present invention, and detailed implementation and specific operation process are provided, but the protection scope of the present invention is not limited to the following implementation example.

[0016] figure 1 A block diagram of a preferred embodiment data prefetching system in which the present invention can be implemented is shown. As shown in the figure, the data prefetching module F5 includes a writing unit F3, a register file and a reading unit F6. In the register file of the processor, there are two prefetch registers R_a and R_b, which are called prefetch register groups, namely figure 1 Middle F1. The prefetch registers R_a and R_b have the same structure and function, can be written by the data prefetch module, and are directly used as the source operand by the instruction of the processor. Th...

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Abstract

The invention discloses a data prefetch system in video processing, which includes a data prefetch module, a prefetch register group, a control bus, and a data bus. The data prefetch module is used to control the sequence of data read and write according to the settings of the processor , the prefetch register is used to store the data written by the data prefetch module for the processor to read, and can only be written by the data prefetch module, the control bus is used to set the data prefetch module, and the data bus is used to connect the data prefetch module Fetch module and prefetch register, wherein: the data prefetch module can directly write data into the prefetch register group of the register file of the processor according to the setting of the processor, and the processor can directly use these prefetch registers in the instruction register to get the required data. Since the processor can directly use these prefetch registers in the instructions to obtain the required data, the instructions for reading data are reduced, and the time for reading block data in video processing is shortened, thereby improving the efficiency of the processor.

Description

technical field [0001] The invention relates to a system in the technical field of telecommunications, in particular to a data prefetch system in video processing. Background technique [0002] In recent years, in order to alleviate the gap between the high-speed processor and the memory, the processor system usually adopts the high-speed cache technology. Cache is a high-speed cache processor, which is located between the CPU and the memory, and is used to store data or instructions recently used by the processor. When the processor accesses data or instructions, it first accesses the cache to check whether the data or instructions to be accessed are in the cache. If the data is in the cache, that is, a cache hit, it directly reads the data and instructions in the cache. If the data or instruction to be accessed by the processor is not in the cache, a cache failure will occur. At this time, the processor will issue an access request to the memory to search for the instruct...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06T1/20G06T1/60
Inventor 贺迅杨华郑素贞方向忠张重阳
Owner SHANGHAI JIAOTONG UNIV