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A stacking type wafer packaging structure

A chip packaging and stacking technology, applied in semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., can solve the problems of height reduction and compactness, and achieve the effect of reducing height and compacting volume

Inactive Publication Date: 2009-08-05
CHIPMOS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, since the spacer 140 is disposed in the stacked chip package structure 100, its height cannot be reduced, and the requirement of compactness cannot be met.

Method used

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  • A stacking type wafer packaging structure
  • A stacking type wafer packaging structure
  • A stacking type wafer packaging structure

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Experimental program
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Effect test

Embodiment Construction

[0042] figure 2 is a schematic cross-sectional view of the first embodiment of the stacked chip package structure of the present invention. See figure 2The stacked chip package structure 200 of the present invention mainly includes a substrate 210 , a first chip 220 , a plurality of bonding wires 230 , a second chip 240 and a plurality of conductive bumps 250 with B-level characteristics. A plurality of first solder pads 212 and a plurality of second solder pads 214 are respectively disposed on the first surface 210 a and the second surface 210 b of the substrate 210 . The first chip 220 is disposed on the first surface 210 a of the substrate 210 , and a plurality of third bonding pads 222 are disposed on the active surface 220 a. In an embodiment of the present invention, the first chip 220 is adhered on the substrate 210 through an adhesive layer 260 . However, the first chip can also be fixed on the substrate 210 by other methods, and the present invention does not imp...

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Abstract

The present invention relates to a stacked chip packaging structure, which includes a substrate, a first chip, a plurality of bonding wires, a second chip and a plurality of B-stage conductive bumps with B-stage characteristics . Wherein, the first chip is arranged on the substrate, and the first welding pad is arranged on the active surface thereof. In addition, the first welding pad is electrically connected to the substrate through the bonding wire. The second wafer is disposed above the first wafer, and a plurality of second welding pads are disposed on the active surface thereof. The second bonding pads on the second chip are electrically connected to the first bonding pads of the first chip via respective conductive bumps with B-level characteristics, and each conductive bump with B-level characteristics covers the corresponding bonding wire part of the wire.

Description

technical field [0001] The present invention relates to a chip package structure, and in particular to a stacked chip package structure. Background technique [0002] In today's highly informationized society, the market for multimedia applications continues to expand rapidly. Integrated circuit packaging technology also needs to cooperate with the digitalization, networking, regional connection and user-friendly development of electronic devices. In order to meet the above requirements, it is necessary to strengthen the requirements of high-speed processing, multi-functionality, accumulation, miniaturization, weight reduction and low price of electronic components. Therefore, different types of high-density packages have been developed, such as Ball grid arrays (BGA), Chip Scale Package (CSP), Flip Chip and stacked multi-chip packages. Packaging modules. [0003] figure 1 is a schematic cross-sectional view of a conventional stacked chip package structure. See figure ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L25/00H01L23/488
CPCH01L2924/15311H01L2224/48091H01L2924/0002H01L2224/73265H01L2224/16145H01L2224/32145H01L2224/48227H01L2224/32225H01L2224/73207H01L2924/00014H01L2924/00
Inventor 沈更新
Owner CHIPMOS TECH INC
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