Page-buffer and non-volatile semiconductor memory including page buffer

A non-volatile, memory technology, used in static memory, read-only memory, memory systems, etc., to solve problems such as occupying space resources

Active Publication Date: 2009-08-12
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The relatively large number of wires must be accommodated by the bus area of ​​the device's large layout area, occupying valuable space resources

Method used

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  • Page-buffer and non-volatile semiconductor memory including page buffer
  • Page-buffer and non-volatile semiconductor memory including page buffer
  • Page-buffer and non-volatile semiconductor memory including page buffer

Examples

Experimental program
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Embodiment Construction

[0058] In the following, the invention will be illustrated by means of preferred but non-limiting examples.

[0059] Figure 11 A block diagram of a nonvolatile semiconductor memory device according to an embodiment of the present invention is shown.

[0060] refer to Figure 11 , the nonvolatile semiconductor memory device of this example includes a memory cell array MCARR, a page buffer block NWPBB, first and second global input lines GDI and nGDI, a global output line GDOUT, a y address signal line Yp , Yq and Yr, read latch signal line LCH, and page buffer decoder NWDE.

[0061] The memory cell array MCARR includes a matrix array of memory cells, word lines WL (not in Figure 11 shown in ) and bit lines BL. In the example of this embodiment, the memory cells are flash memory cell transistors.

[0062] Connect the internal input lines IDI and nIDI, and the internal output line IDOUT between the page buffer decoder NWDE and the corresponding page buffer blo...

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PUM

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Abstract

In one aspect, a non-volatile memory device operable in a program mode and a read mode is provided. The memory device includes a memory cell array having a plurality of nonvolatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device also includes internal data output lines for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between the bit lines of the memory cell array and the internal data output lines. The page buffer includes a sense node selectively connected to a bit line, a latch circuit having a latch node selectively connected to the sense node, a latch that sets a logic voltage of the latch node in a program mode and a read mode An input path, and a latch output path that is separated from the latch input path and sets a logic voltage of an internal data output line according to a logic voltage of a latch node.

Description

technical field [0001] The present invention relates generally to a semiconductor memory device, and more particularly, the present invention relates to page buffer circuits and other circuits used in nonvolatile semiconductor memory devices. Background technique [0002] In recent years, the demand for electrically programmable and electrically erasable nonvolatile memory devices has increased dramatically. Such devices are characterized, at least in part, by their ability to maintain stored data even in the absence of supplied power. The use of so-called flash memory has become very widespread, particularly but not exclusively, in the context of portable devices such as digital cameras, cellular telephones, personal data assistants (PDAs), and laptop computers. A flash memory such as a NAND type is capable of storing a large amount of data in a relatively small area. [0003] As discussed in the background, the underlying basic principles of operation of flash memory cel...

Claims

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Application Information

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IPC IPC(8): G11C16/06G06F12/00
Inventor 李城秀林瀛湖赵显哲蔡东赫
Owner SAMSUNG ELECTRONICS CO LTD
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