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Reset device of test accesses terminal port of JTAG chain circuit used on board

A reset device and single-board technology, which is applied in the direction of measuring devices, electronic circuit testing, measuring electricity, etc., can solve problems such as difficult selection of pull-down resistors, unstable JTAG chips, and excessive resistance.

Inactive Publication Date: 2009-08-19
NANJING ZHONGXING XIN SOFTWARE CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But its disadvantage is that when the resistance selection in this method is unreasonable, it will limit the use of the BST boundary scan test function, and the JTAG chip will not enter an unstable state when the single board in the direct grounding method is running normally, but this will make the test The BST function used is invalid. If the resistance is too small, the driving ability of the BST test equipment is required to be strong. If the resistance is too large, it will not cause problems with the BST test function. The chip enters an unstable state
Generally, the TRST port of a JTAG device has a pull-up resistor inside the chip. When the length of the daisy chain (that is, the number of JTAG devices on the JTAG daisy chain) is different, the selection of this pull-down resistor is difficult to unify.

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  • Reset device of test accesses terminal port of JTAG chain circuit used on board
  • Reset device of test accesses terminal port of JTAG chain circuit used on board
  • Reset device of test accesses terminal port of JTAG chain circuit used on board

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Embodiment Construction

[0016] The specific implementation manners of the present invention will be described in detail below with reference to the accompanying drawings.

[0017] The IEEE1149.1-1990 standard stipulates that the hardware of the device test access port TAP with JTAG test function consists of four pins TDI, TDO, TMS, and TCK, and an optional test reset pin TRST. The functions of these test signals are described as follows:

[0018] TCK: Test Clock (Test Clock), which is an input signal, has nothing to do with the system clock and is an independent clock source.

[0019] TMS: Test Mode Select.

[0020] TDO: Test Date Output.

[0021] TDI: Test Date input.

[0022] TRST: Test Reset (Test Reset), TRST is an asynchronous reset input signal, active low. Usually TRST is '1', and when it is reset asynchronously, a '0' signal that lasts long enough is generated on the TRST input line to reset the TAP controller asynchronously. TRST is an option signal. Not all JTAG device TAP ports have ...

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Abstract

The invention discloses a reset device for a test access port of a JTAG link on a single board. The module is used to make the JTAG socket debug the single board, the level change of the interface of the JTAG device will not reset the external device by mistake; and the reset circuit is used to provide a valid reset pulse to the external device, and provide the reset pulse to the external device through the isolation module. Daisy-chaining of JTAG devices. Through the invention, the TAP port of the JTAG chip can reliably enter the correct state under the two states of BST test state and normal power-on reset state.

Description

technical field [0001] The invention relates to the field of electronic equipment, in particular to a reset device for a test access port of a JTAG link on a single board. Background technique [0002] There are more and more pins in large-scale integrated circuits. The traditional probe test method and bed of nails test method have considerable difficulties in PCB layout and single-board production test. For example, the addition of test points may cause line impedance. Continuous, BGA-packaged chip test points are difficult to set and other issues. In order to solve the problems faced by PCB testing, the Joint Test Action Group (JTAG) drafted the IEEE1149.1 standard in 1990, integrating hardware resources required for some testing and programmable chip program downloads. In the chip, it provides convenience for users to solve the problems of testing and chip program download. Later, several standards such as IEEE1149.4 and IEEE1149.6 supported the JTAG port of the chip t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R1/30G01R31/28H03K17/22
Inventor 石晶
Owner NANJING ZHONGXING XIN SOFTWARE CO LTD