Reset device of test accesses terminal port of JTAG chain circuit used on board
A reset device and single-board technology, which is applied in the direction of measuring devices, electronic circuit testing, measuring electricity, etc., can solve problems such as difficult selection of pull-down resistors, unstable JTAG chips, and excessive resistance.
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment Construction
[0016] The specific implementation manners of the present invention will be described in detail below with reference to the accompanying drawings.
[0017] The IEEE1149.1-1990 standard stipulates that the hardware of the device test access port TAP with JTAG test function consists of four pins TDI, TDO, TMS, and TCK, and an optional test reset pin TRST. The functions of these test signals are described as follows:
[0018] TCK: Test Clock (Test Clock), which is an input signal, has nothing to do with the system clock and is an independent clock source.
[0019] TMS: Test Mode Select.
[0020] TDO: Test Date Output.
[0021] TDI: Test Date input.
[0022] TRST: Test Reset (Test Reset), TRST is an asynchronous reset input signal, active low. Usually TRST is '1', and when it is reset asynchronously, a '0' signal that lasts long enough is generated on the TRST input line to reset the TAP controller asynchronously. TRST is an option signal. Not all JTAG device TAP ports have ...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 


