Dibit dielectric memory unit array and method for detecting charge stored in the array

Abstract

A method of detecting charge stored in a charge storage region (62) of a first dual-bit dielectric memory cell (49) within an array (40) of dual-bit dielectric memory cells (48), comprising combining a charge with the first memory cell ( The channel region (50) of 49) forms a source junction for the first bit line (201), coupled to the ground line (68). A high voltage is applied to the gate (60) of the first memory cell (49) and the second bit line (202), which is the next bit line to the right of the first bit line (201), and only through the channel region (50) is separated from the first bit line (201). The third bit line (203), which is the next bit line to the right of the second bit line (202), is isolated so that its potential is only affected by its second channel region (50) on the opposite side of the third bit line (203). ) and the junction between the third channel region (50). A high voltage is applied to the pre-charged bit line, located to the right of the third bit line (203), and the current on the second bit line (202) is sensed to determine the source bit (62) of the first memory cell (49) ) programming status.

Description

technical field [0001] The present invention relates to flash memory cell devices, and more particularly, to improvements in pre-charge read methods to read charges previously stored in a dielectric memory cell structure of a dual-bit dielectric memory cell. Background technique [0002] A common type of floating-gate flash memory, electrically erasable programmable read only memory (EEPROMs), utilizes a memory cell characterized by a tunnel oxide (SiO 2 ), a polysilicon floating gate on the tunnel oxide, an interlayer dielectric (typically oxide, nitride, oxide stack) on the floating gate, and a control gate on the interlayer dielectric Stack vertically. Within the substrate, there is a channel region under the vertical stack, and source and drain diffusion regions on opposite sides of the channel region. [0003] The floating gate flash memory cell generates a non-volatile negative charge on the floating gate by inducing hot electron injection from the channel region to ...

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Problems solved by technology

However, even a small voltage difference between bit line 26c and bit line 26d may cause current flow and incorrectly read

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