Crystal wafer for testing aging and electricity performances and construction thereof
A technology of burn-in test and electrical test, applied in the direction of single semiconductor device testing, semiconductor/solid-state device testing/measurement, etc., can solve the problems of difficult simultaneous contact, reduced cost-effectiveness, and high cost
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no. 1 example
[0020] Each die is provided with a built-in aging pattern generating circuit, as long as a voltage source is provided to the die, an aging test pattern (aging pattern) can be generated for aging testing. Please refer to Figure 1A and Figure 1B , which is a schematic diagram of the wafer according to the first embodiment of the present invention. Since there are a large number of dies with the same method on the wafer, for the sake of clarity, six dies with the same method are used here as a representative. Such as Figure 1A As shown in , the wafer 100 includes a first bare die 110 , a first aging pattern generation circuit 120 , electrode pads 130 and scribelines 140 .
[0021] The dicing line 140 is formed on the wafer 100 other than the first die 110 . That is, a dicing line 140 is left between any two adjacent dies on the wafer 100 as a gap for cutting between the dies. After the wafer 100 is diced, only the bare die remains.
[0022] Each burn-in pattern generates a...
no. 2 example
[0027] Please refer to Figure 2A , is a schematic diagram of a wafer according to the second embodiment of the present invention. Such as Figure 2A As shown in , the wafer 200 includes a first die 210, a plurality of second dies 211, a first burn-in pattern generation circuit 220, a plurality of second burn-in pattern generation circuits 221, electrode pads 230, dicing lines 240 and walking Line 250.
[0028] The dicing street 240 is formed on the wafer 200 other than the first die 210 and the second die 211 . That is, a dicing line 240 is left between any two adjacent dies on the wafer 200 as a gap for cutting between the dies. When the wafer 200 is diced, only the bare die remains.
[0029] Each burn-in pattern generating circuit is used for performing burn-in test on the corresponding die, but all burn-in pattern generating circuits are electrically connected with an electrode pad. In the second embodiment, the first burn-in pattern generation circuit 220 is used to ...
no. 3 example
[0035] Only one set of burn-in pattern generating circuits is made on the dicing lane, so that all bare dies can individually generate burn-in test patterns for further burn-in testing. Please refer to Figure 3A , which is a schematic diagram of a wafer according to the third embodiment of the present invention. Such as Figure 3A As shown in , the wafer 300 includes a first die 310 , a plurality of second die 311 , a first burn-in pattern generation circuit 320 , electrode pads 330 , scribe lines 340 and wires 350 .
[0036] The dicing street 340 is formed on the wafer 300 other than the first die 310 and the second die 311 . That is, a dicing line 340 is left between any two adjacent dies on the wafer 300 as a gap for cutting between the dies. When the wafer 300 is diced, only the bare die remains.
[0037] A burn-in test is performed on all dies using an burn-in pattern generation circuit. In the third embodiment, the first die 310 is electrically connected to the first...
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