Making method for grid structure

Abstract

A method for manufacturing a gate structure, comprising: sequentially depositing a dielectric layer, a conductive layer, a barrier layer, and a patterned photoresist layer on a substrate; etching the barrier layer; removing the patterned photoresist The etchant layer: using the first etching gas to etch the upper surface of the conductive layer; using the second etching gas to etch the conductive layer and the dielectric layer. By respectively setting the etching rates of the etching gas on the conductive layer material and the metal layer material oxide on the conductive layer, a certain etching selectivity ratio of the etching gas to the conductive layer material and the metal layer material oxide can be obtained, and finally no Gate structure with root defects.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing a gate structure. Background technique [0002] Semiconductor devices change the electric field strength in the dielectric layer by applying a voltage on the gate, and then control the electric field on the surface of the substrate, and finally change the conductivity of the conductive channel. It can be seen that the performance of the gate is very important to the performance of the semiconductor device, and the performance of the gate is mainly determined by the structure of the gate. [0003] Figure 1A-1D In order to illustrate the device cross-sectional diagram of each step of the manufacturing method of the gate structure in the prior art, as shown in the figure, a manufacturing method of the gate structure provided in the Chinese patent application with the application number "CN97111174.X" is as follows: [0004] First, if ...

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Problems solved by technology

Then, the root defect of the barrier layer will serve as a hard mask for etching the conductive layer and the dielectric layer at the same time, so that the etching gas cannot etch the conductive layer and the dielectric layer under the root defect of the barrier layer, forming a gate root defect

The existence of the root defect of the gate is equivalent to increasing the length of the gate, and the increase of the gate length is likely to cause a decrease in device performance, such as a decrease in drain saturation current, a decrease in threshold voltage, and an increase in interjunction capacitance. will cause device failure

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