Frequency synthesizer

Abstract

A circuit, with applications to phase-locked loops and frequency synthesis, where a divider circuit shuffles between dividing the output of a voltage-controlled oscillator by N or N+1, where N is an integer, and where a phase frequency detector provides three logic signals to a charge pump so that one of three values of current may be sourced to a loop filter, with the result that the circuit behaves as a conventional phase-lockup loop fictitious divider circuit that is capable of dividing the output of the voltage-controlled oscillator by a non-integral value.

Description

technical field [0001] The present invention relates to circuits, and more particularly to frequency synthesizers. Background technique [0002] figure 1 An equivalent circuit diagram 100 of a known technology of a phase-locked loop (Phase-Locked Loop, PLL) is shown. Such as figure 1 As shown, the equivalent circuit diagram 100 of the prior art includes a phase frequency detector (PFD) 110, a charge pump (CP) 120, a loop filter (LF) 130 and a voltage controlled oscillator (VCO) 140 . The phase frequency detector 110 detects the phase difference between a reference clock (REF) and a feedback clock (FB) generated by the voltage controlled oscillator 140 . marked on figure 1 The UP signal and DN signal are usually used by the phase frequency detector 110 to represent the phase difference between the two frequencies. In each phase comparison, UP pulses, DN pulses or both are generated. If the reference clock leads the feedback clock (in other words, the rising edge of the...

AI Technical Summary

Problems solved by technology

[0008] The purpose of the present invention is to provide a fractional N frequency synthesizer circuit and method thereof, to solve the aforementioned problems

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