Method for reducing flash ROM setting time and improved flash memory

Abstract

This invention relates to a method for biasing word lines in a flash memory array, in which, the word lines are selected to be used in reading operation in the period of accessing data, and the method includes: biasing un-selected word lines with the un-selected word line voltage, delaying a time period and biasing said selected lines to execute said read operation with the voltage of the selected lines.

Description

technical field [0001] The present invention generally relates to flash memory devices and methods of reading data therefrom. Background technique [0002] Negative and (NAND) type EEPROM (Electrically Erasable Programmable Read-Only Memory) or flash memory has been developed for solid-state mass storage applications in portable music players, mobile phones, digital cameras, etc., and it has been considered as a Hard Disk Drive (HDD) replacement. [0003] The long RC delays associated with the long and narrow polysilicon word lines of flash memory arrays must be taken into account when reading data from the array. Parasitic capacitance as well as wordline-to-wordline capacitance provide RC delay because the selected wordline initially couples to a higher voltage adjacent to the unselected wordline, which means that an accurate read cannot be done until the selected wordline dissipates this coupling Voltage. The coupling effect becomes especially strong between closely spa...

AI Technical Summary

Problems solved by technology

Although at least conceptually metal shunts can be used to reduce RC delay, the use of metal shunts is generally not preferred because of the additional cost associated with it and the difficulty of providing shunt metal in such a narrow spacing

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