Digital signal processor with dynamic submitting pipeline function

Abstract

This invention discloses one digital signal processor with dynamic streamline function, wherein, the inner rack comprises program control unit, order code unit, register file, execution unit and the transfer control bench for management order; the said frame control unit is connected to code unit and transfer control bench; the transfer control bench and register file data are connected; the code unit is connected to the register file and execution unit ; the execution unit is connected to the register file data. This invention adds order transfer control bench on process system into code unit to identify whether the current order is abnormal.

Description

Technical field: [0001] The invention relates to a general digital signal processor, in particular to a digital signal processor with the function of dynamically submitting pipelines. Background technique: [0002] At present, in the design of high-performance digital signal processors, pipeline technology occupies a very important position in performance. In the current popular processors, the combination of scheduling and predictive execution based on Tomasulo algorithm is widely used (such as PowerPC 620, MIPS R10000, etc.). [0003] The important idea of ​​implementing this method is to allow instructions to be executed out of order but must be submitted in order, and any unrecoverable behavior should be avoided before the instruction is submitted. Different from the general DLX pipeline, implementing this method needs to add an extra step, that is, instruction submission. Adding the commit state not only requires that the instruction execution sequence can be changed,...

AI Technical Summary

Problems solved by technology

[0014] Now assuming that it takes 8 execution cycles to execute the division instruction, and there are 8 virtual registers idle in the hardware, it can be seen that it takes 17 instruction cycles to execute this program, and a large number of waiting state

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